Systems and methods for a robust double node upset tolerant latch
View Patent ↗Disclosed are a latch circuit and method for preventing double node upsets (DNUs). A first, second, and third storage circuit, each comprising four inputs and an output, are electrically interconnected with a first and second three-input c-element circuit, each comprising three inputs and an output, and a two-input c-element circuit comprising two inputs and an output. The output of the first storage circuit is connected to a first input of the first three-input c-element circuit, a first input of the third storage circuit and a third input of the second storage circuit. The output of the second storage circuit is connected to a second input of the first three-input c-element circuit, a first input of the two-input c-element circuit, and a second input of the second three-input c-element circuit. The output of the third storage circuit is connected to a second input of the two-input c-element circuit, a third input of the first three-input c-element circuit and a third input of the second three-input c-element circuit.
1. A double node upset (DNU) tolerant latch circuit comprising:
a first storage circuit, a second storage circuit, and a third storage circuit, each comprising four inputs and an output;
a first three-input c-element circuit comprising three inputs and an output; and
a first two-input c-element circuit comprising two inputs and an output,
wherein the output of the first storage circuit is electrically connected to a first input of the first three-input c-element circuit and a first input of the third storage circuit, the output of the second storage circuit is electrically connected to a second input of the first three-input c-element circuit and a first input of the first two-input c-element circuit, and the output of the third storage circuit is electrically connected to a second input of the first two-input c-element circuit and a third input of the first three-input c-element circuit, the output of the third storage circuit comprising the output of the DNU tolerant latch circuit.
2. The DNU tolerant latch circuit of claim 1 further comprising:
a second three-input c-element circuit comprising three inputs and an output, where the output of the second three-input c-element circuit is electrically connected to a first input of the first storage circuit, a first input of the second storage circuit, and a second input of the third storage circuit.
3. The DNU tolerant latch circuit of claim 2 further comprising:
a second two-input c-element circuit comprising two input and an output, where the output of the second two-input c-element circuit is electrically connected to a second input of the second storage circuit, a first input of the second three-input c-element circuit, and a third input of the third storage circuit.
4. The DNU tolerant latch circuit of claim 3 wherein the output of the first storage circuit is further electrically connected to a third input of the second storage circuit.
5. The DNU tolerant latch circuit of claim 3 wherein the output of the second storage circuit is further electrically connected to a second input of the second three-input c-element circuit.
6. The DNU tolerant latch circuit of claim 3 wherein the output of the third storage circuit is further electrically connected to a third input of the second three-input c-element circuit.
7. The DNU tolerant latch circuit of claim 3 wherein the output of the first three-input c-element is electrically connected to a fourth input of the third storage circuit, a first input of the second two-input c-element circuit, and a fourth input of the second storage circuit.
8. The DNU tolerant latch circuit of claim 3 wherein the output of the first two-input c-element circuit is further electrically connected to a second input of the first storage circuit and a second input of the second two-input c-element circuit.
9. The DNU tolerant latch circuit of claim 3 wherein each of the first storage circuit, the second storage circuit, and the third storage circuit comprises a four-input c-element circuit and a latch.
10. The DNU tolerant latch circuit of claim 9 wherein the four-input c-element circuit of the first storage circuit, the second storage circuit, and the third storage circuit comprises a plurality of transistor devices connected in series, the plurality of transistor devices comprising a first subset of PMOS transistors and a second subset of NMOS transistors.
11. The DNU tolerant latch circuit of claim 3 wherein each of the first three-input c-element circuit and the second three-input c-element circuit comprises four transistor devices connected in series, a first subset of the four transistor devices comprising PMOS transistors and a second subset of the four transistor devices comprising NMOS transistors.
12. The DNU tolerant latch circuit of claim 1 wherein a third input of the first storage circuit is electrically connected to a clock signal.
13. A method for preventing double node upsets (DNUs) in a latch circuit, the method comprising:
electrically interconnecting:
a first storage circuit, a second storage circuit, and a third storage circuit, each comprising four inputs and an output;
a first three-input c-element circuit and a second three-input c-element circuit, each comprising three inputs and an output; and
a first two-input c-element circuit comprising two inputs and an output;
wherein the output of the first storage circuit is electrically connected to a first input of the first three-input c-element circuit, a first input of the third storage circuit and a third input of the second storage circuit; the output of the second storage circuit is electrically connected to a second input of the first three-input c-element circuit, a first input of the first two-input c-element circuit, and a second input of the second three-input c-element circuit; and the output of the third storage circuit is electrically connected to a second input of the first two-input c-element circuit, a third input of the first three-input c-element circuit and a third input of the second three-input c-element circuit.
14. The method of claim 13 wherein the output of the second three-input c-element circuit is electrically connected to a first input of the first storage circuit, a first input of the second storage circuit, and a second input of the third storage circuit.
15. The method of claim 14 further comprising:
electrically connecting a second two-input c-element circuit comprising two input and an output, wherein the output of the second two-input c-element circuit electrically connected to a second input of the second storage circuit, a first input of the second three-input c-element circuit, and a third input of the third storage circuit.
16. The method of claim 15 wherein the output of the first three-input c-element is electrically connected to a fourth input of the third storage circuit, a first input of the second two-input c-element circuit, and a fourth input of the second storage circuit.
17. The method of claim 15 wherein the output of the first two-input c-element circuit is further electrically connected to a second input of the first storage circuit and a second input of the second two-input c-element circuit.
18. The method of claim 15 wherein the four-input c-element circuit of the first storage circuit, the second storage circuit, and the third storage circuit comprises a plurality of transistor devices connected in series, the plurality of transistor devices comprising a first subset of PMOS transistors and a second subset of NMOS transistors.
19. The method of claim 15 wherein each of the first three-input c-element circuit and the second three-input c-element circuit comprises four transistor devices connected in series, a first subset of the four transistor devices comprising PMOS transistors and a second subset of the four transistor devices comprising NMOS transistors.
20. The method of claim 13 wherein each of the first storage circuit, the second storage circuit, and the third storage circuit comprises a four-input c-element circuit and a latch.