Semiconductor package having junction cooling pipes embedded in substrates
View Patent ↗Implementations of semiconductor packages may include a first substrate coupled to a first die, a second substrate coupled to a second die, and a spacer included within a perimeter of the first substrate and within a perimeter of a second substrate, the spacer coupled between the first die and the second die, the spacer include a junction cooling pipe therethrough.
1. A semiconductor package comprising:
a first substrate coupled to a first die;
a first plurality of junction cooling pipes, each junction cooling pipe of the first plurality of junction cooling pipes at least partially embedded in the first substrate;
a second substrate coupled to a second die;
a second plurality of junction cooling pipes, each junction cooling pipe of the second plurality of junction cooling pipes at least partially embedded in the second substrate; and
a spacer directly coupled, through a solder, to and between the first die and the second die;
wherein a perimeter of the spacer fits within a perimeter of the first die and within a perimeter of the second die.
2. The package of claim 1 , wherein the first substrate and the second substrate comprise one of a dielectric layer, a patterned layer, or both a dielectric layer and a patterned layer.
3. The package of claim 1 , wherein the first plurality of junction cooling pipes is fully embedded in the first substrate.
4. The package of claim 1 , wherein the second plurality of junction cooling pipes is fully embedded in the second substrate.
5. The package of claim 1 , wherein the first plurality of junction cooling pipes and the second plurality of junction cooling pipes each comprise one of heat pipes, water pipes, or a combination of heat pipes and water pipes.
6. The package of claim 1 , wherein each pipe of the first plurality of junction cooling pipes and each pipe of the second plurality of junction cooling pipes are coated with a dielectric material.
7. A semiconductor package comprising:
a first substrate coupled to a first die;
a first plurality of junction cooling pipes, each junction cooling pipe of the first plurality of junction cooling pipes fully embedded in the first substrate;
a second substrate coupled to a second die;
a second plurality of junction cooling pipes, each junction cooling pipe of the second plurality of junction cooling pipes fully embedded in the second substrate; and
a spacer directly coupled, through a solder, to and between the first die and the second die;
wherein a perimeter of the spacer fits within a perimeter of the first die and within a perimeter of the second die.
8. The package of claim 7 , wherein the first substrate and the second substrate comprise a dielectric layer.
9. The package of claim 7 , wherein the first substrate and the second substrate comprise a patterned layer.
10. The package of claim 7 , wherein the first substrate and the second substrate comprise both a dielectric layer and a patterned layer.
11. The package of claim 7 , wherein the first plurality of junction cooling pipes and the second plurality of junction cooling pipes each comprise heat pipes.
12. The package of claim 7 , wherein the first plurality of junction cooling pipes and the second plurality of junction cooling pipes each comprise water pipes.
13. The package of claim 7 , wherein the first plurality of junction cooling pipes and the second plurality of junction cooling pipes each comprise a combination of heat pipes and water pipes.
14. The package of claim 7 , wherein each pipe of the first plurality of junction cooling pipes and each pipe of the second plurality of junction cooling pipes are coated with a dielectric material.