2T1C ferro-electric random access memory cell
View Patent ↗A memory device and method of operating the same are disclosed. Generally, the device includes an array of Ferro-electric Random Access Memory cells. Each cell includes a first transistor coupled between a bit-line and a storage node (SN) and controlled by a first wordline (WL 1 ), a second transistor coupled between a reference line and the SN and controlled by a second wordline (WL 2 ), and a ferro-capacitor coupled between the SN and a plateline. The device further includes a sense-amplifier coupled to the bit-line and reference line, and a processing-element configured to issue control signals to WL 1 , WL 2 , the plateline and the sense-amplifier. The cell is configured and operated to generate a bit-level reference in which a first voltage pulse is applied to the plateline during a read cycle for the data pulse and a second voltage pulse serves as a reference pulse and as a clear pulse.
1. A memory device comprising:
an array of Ferro-electric Random Access Memory (F-RAM) cells, at least one F-RAM cell comprising:
a first transistor coupled between a bit-line and a storage node (SN);
a second transistor coupled between a reference line and the SN; and
a ferro-capacitor coupled between the SN and a plateline,
wherein the F-RAM cell is configured to generate a bit-level reference in which a reference voltage on the reference line compared to a data voltage on the bit-line during a read cycle is derived from an unswitched (U-term) of the ferro-capacitor of the same F-RAM cell.
2. The memory device of claim 1 , further comprising:
a sense-amplifier (SA) coupled to the bit-line and the reference line to compare to the reference voltage on the reference line to the data voltage on the bit-line; and
a processing-element configured to issue control signals to the first transistor, second transistor and the SA, and to apply voltage pulses to the plateline,
wherein the processing-element is configured during the read cycle to apply a first voltage pulse with a first peak voltage (V1) to the plateline to couple data from SN to the bit-line, and a second voltage pulse with a second peak voltage (V2) to the plateline to couple the reference voltage to the reference line and to serve as a clear pulse to harden the U-term in the ferro-capacitor.
3. The memory device of claim 2 , wherein the plateline, reference line and second transistor are configured so that the reference voltage tracks changes in the U-term of the ferro-capacitor of the same F-RAM cell.
4. The memory device of claim 2 , wherein the bit-line capacitance is substantially equal to a reference line capacitance.
5. The memory device of claim 4 , wherein the processing-element is configured so that V2 is greater than V1.
6. The memory device of claim 4 , wherein the processing-element is configured to sweep the voltage V2 of the second voltage pulse from zero volts to greater than V1.
7. The memory device of claim 2 , wherein the bit-line capacitance is greater than a reference line capacitance.
8. The memory device of claim 2 , further comprising:
a bit-line pre-charge circuit controlled by the processing-element and configured to pre-charge and release the bit-line prior to the first voltage pulse; and
a reference line pre-charge circuit controlled by the processing-element and configured to discharge any residual voltage on the SN and release the reference line prior to the second voltage pulse.
9. The memory device of claim 8 , wherein the bit-line pre-charge circuit and the processing-element are further configured to discharge any residual voltage on the SN prior to the first voltage pulse.
10. The memory device of claim 9 , wherein the F-RAM cell is configured so that the bit-line pre-charge circuit remains electrically decoupled from the bit-line during the read cycle between the first voltage pulse and the second voltage pulse.
11. A memory device comprising:
an array of Ferro-electric Random Access Memory (F-RAM) cells, at least one F-RAM cell comprising:
a first transistor coupled between a bit-line and a storage node (SN);
a second transistor coupled between a reference line and the SN; and
a ferro-capacitor coupled between the SN and a plateline;
a sense-amplifier (SA) coupled to the bit-line and the reference line to compare a data voltage on the bit-line to a reference voltage on the reference line; and
a processing-element configured to issue control signals to the first transistor, second transistor and the SA, and to apply voltage pulses to the plateline,
wherein the F-RAM cell is configured to generate a bit-level reference in which two voltage pulses are applied to the plateline during a read cycle, and wherein a first of the two voltage pulses is used as a data pulse and a second of the two pulses is used as a reference pulse to couple the reference voltage to the reference line and as a clear pulse to harden an unswitched (U-term) in the ferro-capacitor.
12. The memory device of claim 11 , wherein the processing-element is configured to during the read cycle apply a first voltage pulse with a first peak voltage (V1) to the plateline to couple data from SN to the bit-line, and a second voltage pulse with a second peak voltage (V2) to the plateline to couple the reference voltage to the reference line and as a clear pulse to harden the U-term in the ferro-capacitor.
13. The memory device of claim 12 , wherein the processing-element is configured so that V2 is greater than V1.
14. The memory device of claim 13 , wherein the processing-element is configured to sweep the voltage V2 of the second voltage pulse from zero volts to greater than V1.
15. The memory device of claim 11 , wherein the plateline, reference line and second transistor are configured so that the reference voltage tracks changes in the U-term of the ferro-capacitor of the same F-RAM cell.
16. The memory device of claim 11 , further comprising a bit-line pre-charge circuit a controlled by the processing-element and configured to pre-charge and release the bit-line prior to the first voltage pulse, and wherein the F-RAM cell is configured so that the bit-line pre-charge circuit remains electrically decoupled from the bit-line during the read cycle between the first voltage pulse and the second voltage pulse.
17. A memory device comprising:
a Ferro-electric Random Access Memory (F-RAM) cell comprising:
a first transistor coupled between a bit-line and a storage node (SN) and controlled by a first wordline (WL 1 );
a second transistor coupled between a reference line and the SN and controlled by a second wordline (WL 2 ); and
a ferro-capacitor coupled between the SN and a plateline;
a sense-amplifier coupled to the bit-line and the reference line; and
a processing-element configured to issue control signals to WL 1 , WL 2 and the sense-amplifier, and to apply voltage pulses to the plateline,
wherein the processing-element is configured to during a read cycle apply a first voltage pulse with a first peak voltage (V1) to the plateline to couple a data voltage from SN to the bit-line, and a second voltage pulse with a second peak voltage (V2) to the plateline to couple a reference voltage to the reference line and as a clear pulse to harden an unswitched (U-term) in the ferro-capacitor.
18. The memory device of claim 17 , wherein the processing-element is configured to sweep the voltage V2 of the second voltage pulse from zero volt to greater than V1.
19. The memory device of claim 17 , wherein the reference voltage is derived from the U-term of the ferro-capacitor of the same F-RAM cell, and the plateline, reference line and second transistor are configured so that the reference voltage tracks changes in the U-term.
20. The memory device of claim 17 , further comprising a bit-line pre-charge circuit controlled by the processing-element and configured to pre-charge and release the bit-line prior to the first voltage pulse, and wherein the F-RAM cell is configured so that the bit-line pre-charge circuit remains electrically decoupled from the bit-line during the read cycle between the first voltage pulse and the second voltage pulse.