Pseudo single pass NAND memory programming
Embodiments include apparatuses, methods, and computer devices including a multi-level NAND memory array and a memory controller coupled to the multi-level NAND memory array. The multi-level NAND memory array may include a first word line and a second word line. The memory controller may receive a first page of data and a second page of data together with a program command to program the first page of data and the second page of data into the multi-level NAND memory array. The memory controller may program the first page of data into a page of the first word line via a first pass, and further program the second page of data into a page of the second word line via a second pass, subsequent to the first pass. Other embodiments may also be described and claimed.
1. An apparatus for computing, comprising:
a multi-level NAND memory array including a first word line and a second word line;
a memory controller coupled to the multi-level NAND memory array, wherein the memory controller is to:
receive a first page of data and a second page of data together with a program command from a host controller to program the first page of data and the second page of data into the multi-level NAND memory array, wherein the first page of data, the second page of data, and the program command are programmed by the host controller in a single pass at a same time;
program the first page of data into a page of the first word line via a first pass in the NAND memory array; and
program the second page of data into a page of the second word line via a second pass in the NAND memory array, subsequent to the first pass.
2. The apparatus of claim 1 , wherein the multi-level NAND memory array is a three or higher level NAND memory array, the multi-level NAND memory array further includes a third word line, and the memory controller is further to:
receive, a third page of data together with the first page of data, the second page of data, and the program command to program the first page of data, the second page of data, and the third page of data into the multi-level NAND memory array; and
program the third page of data into a page of the third word line via a third pass.
3. The apparatus of claim 2 , wherein the third word line is the first word line and the third pass is the first pass, or the third word line is the second word line and the third pass is the second pass.
4. The apparatus of claim 1 , wherein the multi-level NAND memory array is an n level NAND memory array, the multi-level NAND memory array includes multiple word lines that include the first word line and the second word line, and the memory controller is further to:
receive m pages of data that include the first page of data and the second page of data together with the program command to program the m pages of data into the n level NAND memory array; and
program the m pages of data into pages of the multiple word lines, via multiple passes, wherein n>3, and n>=m>=2.
5. The apparatus of claim 1 , wherein the first word line and the second word line are in a same block of the multi-level NAND memory array.
6. The apparatus of claim 1 , wherein the first word line is in a first plane, a first die, or a first block of the multi-level NAND memory array, and the second word line is in a second plane, a second die, or a second block of the multi-level NAND memory array.
7. The apparatus of claim 1 , wherein the memory controller is further to:
report a cumulative pass or failure status for the program command to program the first page of data and the second page of data.
8. The apparatus of claim 1 , wherein the multi-level NAND memory array is a three level NAND memory array, the first page of data is programmed into a lower page of the first word line, and the second page of data is programmed into an upper page or an extra page of the second word line.
9. The apparatus of claim 1 , wherein the page of the first word line has a size in a range of about 8 kB to about 16 kB, and the page of the first word line is contained in a block of a size of about 4 MB to about 100 MB.
10. The apparatus of claim 1 , wherein the apparatus is a storage device, and the program command is from an external computing device coupled to the storage device.
11. The apparatus of claim 1 , wherein apparatus is a computing system, and the program command is from a processor of the computing system.
12. An electronic system, comprising:
a host controller, wherein the host controller is to generate a first page of data, a second page of data, and a program command to program the first page of data and the second page of data into a multi-level NAND memory array within a NAND memory system; and
the NAND memory system coupled to the host controller, wherein the NAND memory system includes:
the multi-level NAND memory array including a first word line and a second word line; and
a memory controller coupled to the host controller and the multi-level NAND memory array, wherein the memory controller is to:
receive the first page of data, the second page of data, together with the program command from the host controller in a single pass at a same time;
program the first page of data into a page of the first word line via a first pass in the NAND memory array; and
program the second page of data into a page of the second word line via a second pass in the NAND memory array, subsequent to the first pass.
13. The electronic system of claim 12 , wherein:
the host controller is to generate a third page of data, and the program command is to program the first page of data, the second page of data, and the third page of data into the multi-level NAND memory array; and
the multi-level NAND memory array is a three or higher level NAND memory array, the multi-level NAND memory array further includes a third word line, and the memory controller is further to:
receive the third page of data together with the first page of data, the second page of data, and the program command from the host controller; and
program the third page of data into a page of the third word line via a third pass.
14. The electronic system of claim 13 , wherein the third word line is the first word line and the third pass is the first pass, or the third word line is the second word line and the third pass is the second pass.
15. The electronic system of claim 12 , wherein:
the host controller is to generate m pages of data that include the first page of data and the second page of data, and the program command is to program the m pages of data into the multi-level NAND memory array;
the multi-level NAND memory array is an n level memory array, the multi-level NAND memory array includes multiple word lines that include the first word line and the second word line, and the memory controller is further to:
receive the m pages of data together with the program command from the host controller; and
program them pages of data into pages of the multiple word lines, via multiple passes, wherein n>3, and n>=m>=2.
16. The electronic system of claim 12 , wherein the first word line and the second word line are in a same block of the multi-level NAND memory array.
17. The electronic system of claim 12 , wherein the first word line is in a first plane, a first die, or a first block of the multi-level NAND memory array, and the second word line is in a second plane, a second die, or a second block of the multi-level NAND memory array.
18. One or more non-transitory computer-readable media comprising instructions that cause a memory controller, in response to execution of the instructions by the memory controller, to operate the memory controller to:
receive a first page of data, a second page of data, together with a program command from a host controller to program the first page of data and the second page of data into a multi-level NAND memory array coupled to the memory controller, wherein the first page of data, the second page of data, and the program command are programmed by the host controller in a single pass at a same time;
program the first page of data into a page of a first word line of the multi-level NAND memory array via a first pass in the NAND memory array; and
program the second page of data into a page of a second word line of the multi-level NAND memory array via a second pass in the NAND memory array subsequent to the first pass, wherein the multi-level NAND memory array includes the first word line and the second word line.
19. The one or more non-transitory computer-readable media of claim 18 , wherein the memory controller is further caused to:
receive a third page of data together with the first page of data, the second page of data, and the program command to program the first page of data, the second page of data, and the third page of data into the multi-level NAND memory array; and
program the third page of data into a page of a third word line via a third pass, wherein the multi-level NAND memory array is a three or higher level memory array, and the multi-level NAND memory array further includes the third word line.
20. The one or more non-transitory computer-readable media of claim 19 , wherein the third word line is the first word line and the third pass is the first pass, or the third word line is the second word line and the third pass is the second pass.
21. The one or more non-transitory computer-readable media of claim 18 , wherein the memory controller is further caused to:
receive m pages of data that includes the first page of data and the second page of data; wherein the program command is to program the m pages of data into the multi-level NAND memory array; and
program the m pages of data into pages of multiple word lines via multiple passes, wherein the multi-level NAND memory array is an n level memory array, the multi-level NAND memory array includes the multiple word lines that include the first word line and the second word line, n>3, and n>=m>=2.
22. The one or more non-transitory computer-readable media of claim 18 , wherein the first word line and the second word line are in a same block of the multi-level NAND memory array.
23. The one or more non-transitory computer-readable media of claim 18 , wherein the first word line is in a first plane, a first die, or a first block of the multi-level NAND memory array, and the second word line is in a second plane, a second die, or a second block of the multi-level NAND memory array.
24. The one or more non-transitory computer-readable media of claim 18 , wherein the memory controller is within a storage device, and the program command is from an external computing device coupled to the storage device; or the memory controller is within a computing system, and the program command is from a processor of the computing system.
25. The one or more non-transitory computer-readable media of claim 18 , wherein the multi-level NAND memory array is a three level NAND memory array, the first page of data is programmed into a lower page of the first word line, and the second page of data is programmed into an upper page or an extra page of the second word line.