Semiconductor device and display device
View Patent ↗Provided is a semiconductor device that includes: an integrated circuit (IC) chip including a terminal array that is a matrix of terminals arranged in at least seven rows and at least seven columns, the terminals including a reference terminal to which a reference voltage is applied; a capacitor electrically connected to the reference terminal; and a substrate including one main surface as a mounting surface on which the IC chip and the capacitor are mounted. The IC chip is an application specific integrated circuit (ASIC) chip or a field-programmable gate array (FPGA) chip. The reference terminal is disposed at a position within three rows or three columns from an outer edge of the terminal array.
1. A semiconductor device, comprising:
an integrated circuit (IC) chip, configured as an application specific integrated circuit (ASIC) chip or a field programmable gate array (FPGA) chip, including a terminal array that is a matrix of terminals arranged in at least seven rows and at least seven columns, the terminals including a reference terminal to which a reference voltage is applied;
a capacitor electrically connected to the reference terminal; and
a substrate including one main surface as a mounting surface on which the IC chip and the capacitor are mounted,
wherein the reference terminal is disposed at a position within three rows or three columns from an outer edge of the terminal array, and
the reference terminal and the capacitor are connected via a patterned conductor disposed on the mounting surface.
2. A semiconductor device, comprising:
an integrated circuit (IC) chip, configured as an application specific integrated circuit (ASIC) chip or a field programmable gate array (FPGA) chip, including a terminal array that is a matrix of terminals arranged in at least seven rows and at least seven columns, the terminals including a reference terminal to which a reference voltage is applied;
a capacitor electrically connected to the reference terminal; and
a substrate including one main surface as a mounting surface on which the IC chip and the capacitor are mounted,
wherein the reference terminal is not disposed at a position in one of fourth and subsequent rows and one of fourth and subsequent columns from an outer edge of the terminal array,
the reference terminal and the capacitor are connected via a plurality of parallel interconnections connected in parallel, and
wherein the reference terminal and the capacitor are connected via a patterned conductor disposed on the mounting surface.
3. The semiconductor device according to claim 2 ,
wherein at least a portion of the plurality of parallel interconnections is a via interconnection extending in a thickness direction of the substrate.
4. The semiconductor device according to claim 1 , further comprising:
a memory chip mounted on the mounting surface; and
a regulator that is mounted on the mounting surface and supplies the IC chip and the memory chip with the reference voltage,
wherein a distance between the regulator and the memory chip is less than a distance between the regulator and the IC chip.
5. The semiconductor device according to claim 2 , further comprising:
a memory chip mounted on the mounting surface; and
a regulator that is mounted on the mounting surface and supplies the IC chip and the memory chip with the reference voltage,
wherein a distance between the regulator and the memory chip is less than a distance between the regulator and the IC chip.
6. A display device, comprising:
the semiconductor device according to claim 1 .
7. A display device, comprising:
the semiconductor device according to claim 2 .