IP Library › Granted Patent US 10,268,578
Granted Patent B1
US 10,268,578 · App. 15/721,237 · Granted Apr 23, 2019

Data preservation and recovery in a memory component

Inventors: Shankar Natarajan (Santa Clara, CA); Aliasgar S. Madraswala (Folsom, CA); Wayne D. Tran (Folsom, CA)
Assignee: INTEL CORPORATION
G06F12/0804G06F3/065G06F3/068G06F3/0619G06F2212/1024G06F2212/205
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Quick Facts
Patent No.
US 10,268,578
App. No.
15/721,237
Granted
Apr 23, 2019
Kind
B1
Abstract

In one embodiment, a nonvolatile memory of a component such as a storage drive preserves write data in the event of a write data programming failure in the memory. Write data is preserved in the event of cached writes by data preservation logic in registers and data recovery logic recovers the preserved data and outputs the recovered data from the storage drive. Other aspects are described herein.

Claims (44)

1. An apparatus, comprising:

a memory component, the memory component including a bitcell array and a memory controller configured to control memory read and memory write operations directed to the bitcell array, the memory controller including a cache register, a write data register, and a backup register, the memory controller further including:

write logic configured to write a first set of write data to the bitcell array from the write data register, and to cache a second set of write data in a cache register;

data preservation logic configured to transfer the first set of write data from the write data register to a backup data register to preserve the first set of write data in event of a failure to successfully write the first set of write data to the bitcell array wherein the write logic is further configured to copy the second set of write data from the cache register to the write data register after the first set of write data is transferred to the backup register, the data preservation logic being further configured to preserve the second set of write data in the cache register; and

data recovery logic of the memory controller configured to determine whether the first set of write data was successfully written to the bitcell array, and in response to a determination that writing the first set of write data to the bitcell array failed, output the first set of write data preserved in the backup data register.

2. The apparatus of claim 1 wherein the data recovery logic in outputting the preserved first set of write data from the backup data register, is further configured to transfer the preserved first set of write data from the backup data register to the cache register and output the preserved first set of write data from the cache register.

3. The apparatus of claim 2 wherein the write logic is further configured to cache a third set of write data in the cache register after the preserved first set of write data is output from the cache register.

4. The apparatus of claim 1 wherein:

the write logic is further configured to write the second set of write data from the write data register to the bitcell array; and

the data recovery logic is further configured to determine whether the second set of write data was successfully written to the bitcell array, and in response to a determination that writing the second set of write data to the bitcell array failed, output the preserved second set of write data from the cache register.

5. The apparatus of claim 4 wherein the write logic is further configured to cache a third set of write data in the cache register after both outputting the preserved second set of write data from the cache register if writing the second set of write data to the bitcell array failed and after outputting the preserved first set of write data from the cache register.

6. The apparatus of claim 4 wherein the data recovery logic is further configured to transfer the preserved first set of write data from the backup data register to the cache register after the preserved second set of write data is output from the cache register.

7. The apparatus of claim 1 wherein each bitcell of the bitcell array is a single level bitcell configured to store one bit of data.

8. A method, comprising:

write logic of a memory controller of a memory component writing a first set of write data to a bitcell array of the memory component from a write data register;

the write logic caching a second set of write data in a cache register;

data preservation logic of the memory controller transferring the first set of write data from the write data register to a backup data register to preserve the first set of write data in event of a failure to successfully write the first set of write data to the bitcell array;

the write logic copying the second set of write data from the cache register to the write data register after the first set of write data is transferred to the backup data register and preserving the second set of write data in the cache register; and

data recovery logic of the memory controller determining whether the first set of write data was successfully written to the bitcell array, and in response to a determination that writing the first set of write data to the bitcell array failed, outputting the first set of write data preserved in the backup data register.

9. The method of claim 8 wherein the outputting by the data recovery logic of the first set of write data preserved in the backup data register, includes transferring the preserved first set of write data from the backup data register to the cache register and outputting the preserved first set of write data from the cache register.

10. The method of claim 8 further comprising:

the write logic caching a third set of write data in the cache register after outputting the preserved first set of write data from the cache register.

11. The method of claim 9 further comprising:

the write logic writing the second set of write data from the write data register to the bitcell array; and

the data recovery logic determining whether the second set of write data was successfully written to the bitcell array, and in response to a determination that writing the second set of write data to the bitcell array failed, outputting the preserved second set of write data from the cache register.

12. The method of claim 11 further comprising:

the write logic caching a third set of write data in the cache register after both outputting the preserved second set of write data from the cache register if writing the second set of write data to the bitcell array failed and after outputting the preserved first set of write data from the cache register.

13. The method of claim 11 wherein the first set of write data preserved in the backup data register is transferred from the backup data register to the cache register after the second set of write data is output from the cache register.

14. The method of claim 8 wherein each bitcell of the bitcell array is a single level bitcell configured to store one bit of data.

15. A system, comprising:

a central processing unit; and

a memory component, the memory component including a bitcell array and a memory controller configured to control memory read and memory write operations directed to the bitcell array, the memory controller including a cache register, a write data register, and a backup register, the memory controller further including:

write logic configured to write a first set of write data to the bitcell array from the write data register, and to cache a second set of write data in a cache register;

data preservation logic configured to transfer the first set of write data from the write data register to a backup data register to preserve the first set of write data in event of a failure to successfully write the first set of write data to the bitcell array wherein the write logic is further configured to copy the second set of write data from the cache register to the write data register after the first set of write data is transferred to the backup register, the data preservation logic being further configured to preserve the second set of write data in the cache register; and

data recovery logic of the memory controller configured to determine whether the first set of write data was successfully written to the bitcell array, and in response to a determination that writing the first set of write data to the bitcell array failed, output the first set of write data preserved in the backup data register.

16. The system of claim 15 wherein the data recovery logic in outputting the preserved first set of write data from the backup data register, is further configured to transfer the preserved first set of write data from the backup data register to the cache register and output the preserved first set of write data from the cache register.

17. The system of claim 16 wherein the write logic is further configured to cache a third set of write data in the cache register after the preserved first set of write data is output from the cache register.

18. The system of claim 15 wherein:

the write logic is further configured to write the second set of write data from the write data register to the bitcell array; and

the data recovery logic is further configured to determine whether the second set of write data was successfully written to the bitcell array, and in response to a determination that writing the second set of write data to the bitcell array failed, output the preserved second set of write data from the cache register.

19. The system of claim 18 wherein the write logic is further configured to cache a third set of write data in the cache register after both outputting the preserved second set of write data from the cache register if writing the second set of write data to the bitcell array failed and after outputting the preserved first set of write data from the cache register.

20. The system of claim 18 wherein the data recovery logic is further configured to transfer the preserved first set of write data from the backup data register to the cache register after the preserved second set of write data is output from the cache register.

21. The system of claim 15 wherein each bitcell of the bitcell array is a single level bitcell configured to store one bit of data.

22. The system of claim 15 further comprising at least one of: a display communicatively coupled to the central processing unit, a network interface communicatively coupled to the central processing unit, and a battery coupled to provide power to the system.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2023
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP.
Reel/Frame 063815/0490 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 12, 2017
From: NATARAJAN, SHANKAR; MADRASWALA, ALIASGAR S.; TRAN, WAYNE D.
To: INTEL CORPORATION
Reel/Frame 043855/0210 →