Transient voltage suppression diodes with reduced harmonics, and methods of making and using
A semiconductor device includes a semiconductor die. A transient voltage suppression (TVS) structure is formed in the semiconductor die. A capacitor is formed over the semiconductor die. In one embodiment, the capacitor is formed by depositing a first conductive layer over the semiconductor die, depositing an insulating layer over the first conductive layer, and depositing a second conductive layer over the semiconductor die. In another embodiment, the capacitor is formed by forming a trench in the semiconductor die, depositing an insulating material in the trench, and depositing a conductive material in the trench.
1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
forming a transient voltage suppression (TVS) structure in the semiconductor die;
forming a capacitor over the semiconductor die; and
forming a semiconductor package with the TVS structure and capacitor coupled in parallel.
2. The method of claim 1 , further including forming the capacitor by:
depositing a first conductive layer over the semiconductor die;
depositing an insulating layer over the first conductive layer; and
depositing a second conductive layer over the insulating layer.
3. The method of claim 2 , wherein the first conductive layer includes aluminum, and the second conductive layer includes titanium nitride (TiN).
4. The method of claim 1 , further including forming the capacitor by:
forming a trench in the semiconductor die;
depositing an insulating material in the trench; and
depositing a conductive material in the trench over the insulating material.
5. The method of claim 1 , further including forming the TVS structure to include snap-back characteristics.
6. The method of claim 1 , further including forming the semiconductor package to include a plurality of TVS structures.
7. A method of making a semiconductor device, comprising:
providing a semiconductor die including a transient voltage suppression (TVS) structure formed in the semiconductor die; and
forming a capacitor over the semiconductor die.
8. The method of claim 7 , further including forming the capacitor by:
depositing a first conductive layer over the semiconductor die;
depositing an insulating layer over the first conductive layer; and
depositing a second conductive layer over the semiconductor die.
9. The method of claim 8 , wherein the first conductive layer includes aluminum, and the second conductive layer includes titanium nitride (TiN).
10. The method of claim 7 , further including forming the capacitor by:
forming a trench in the semiconductor die;
depositing an insulating material in the trench; and
depositing a conductive material in the trench.
11. The method of claim 7 , further including forming a semiconductor package including the TVS structure and capacitor coupled in parallel.
12. The method of claim 11 , further including coupling the semiconductor package in parallel with a load to protect the load from a transient voltage or electrostatic discharge event.
13. The method of claim 7 , further including forming the TVS structure to include steering diodes.
14. A semiconductor device, comprising:
a semiconductor die including a transient voltage suppression (TVS) structure formed in the semiconductor die;
a capacitor formed over the semiconductor die;
a first interconnect structure formed over the semiconductor die; and
a second interconnect structure formed over the semiconductor die, wherein the TVS structure and capacitor are electrically coupled in parallel between the first interconnect structure and second interconnect structure.
15. The semiconductor device of claim 14 , wherein the capacitor includes:
a first conductive layer formed over the semiconductor die;
an insulating layer formed over the first conductive layer; and
a second conductive layer formed over the insulating layer.
16. The semiconductor device of claim 15 , wherein the first conductive layer includes aluminum and the second conductive layer includes titanium nitride (TiN).
17. The semiconductor device of claim 14 , wherein the capacitor includes:
a trench formed in the semiconductor die;
an insulating material deposited in the trench; and
a conductive material deposited in the trench over the insulating material.
18. The semiconductor device of claim 14 , wherein the semiconductor device includes a plurality of TVS structures packaged together.
19. The semiconductor device of claim 14 , further including an electronic device including a substrate, wherein the TVS structure and capacitor are coupled to a substrate of the electronic device through the first interconnect structure and second interconnect structure.
20. A semiconductor device, comprising:
a semiconductor die including a transient voltage suppression (TVS) structure formed in the semiconductor die; and
a capacitor formed over the semiconductor die.
21. The semiconductor device of claim 20 , wherein the semiconductor die and capacitor are packaged together.
22. The semiconductor device of claim 20 , wherein the capacitor is a metal-insulator-metal (MIM) capacitor.
23. The semiconductor device of claim 20 , wherein the capacitor is a trench capacitor.
24. The semiconductor device of claim 20 , wherein the TVS structure includes steering diodes.
25. The semiconductor device of claim 20 , wherein the TVS structure includes snap-back.