MOSFET and memory cell having improved drain current through back bias application

1. A semiconductor device configured to function as a semiconductor memory device or a transistor with increased on-state drain current, said semiconductor device comprising:

a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type;

a body having said first conductivity type;

a buried layer region interposed between said substrate and said body, wherein a top surface of said buried layer region is lower than a top surface of said body;

a source region and a drain region each having said second conductivity type and being separated by said body; and

said buried layer region separated from said source region and said drain region;

a gate positioned in between said source region and said drain region;

wherein said semiconductor device is configured to function as a memory device upon turning on a bipolar junction transistor (BJT) formed by said buried layer region, said body and one of said source region and said drain region, said memory device having at least two stable states, or as a transistor with increased on-state drain current, upon turning on a lateral bipolar junction (BJT) formed by said source region, said body and said drain region, resulting in increased on-state drain current but with no change in off-state drain current, depending on biases that are applied to said semiconductor device.

2. The semiconductor device of claim 1 , wherein whether said semiconductor device functions as said memory device having at least two stable states, or as said transistor with increased on-state drain current, but with no change in off-state drain current is governed by an amount of voltage applied to said buried layer region.

3. The semiconductor device of claim 1 , wherein a relatively low voltage applied to said buried layer region governs said semiconductor device to function as a MOSFET (metal-oxide-semiconductor field effect transistor) and wherein a relatively high voltage applied to said buried layer region governs said semiconductor device to function as said memory device having at least two stable states.

4. The semiconductor device of claim 3 , wherein a relatively intermediate high voltage applied to said buried layer region higher than said relatively low voltage and lower than said relatively high voltage, but sufficient to turn on said bipolar junction transistor (BJT) formed by said buried layer region, said body and one of said source region and said drain region, turns on said lateral BJT formed by said source region, said body and said drain region, resulting in increased on-state drain current.

5. The semiconductor device of claim 1 , wherein at least one of said source region, drain region and buried layer region has a first junction depth less than a second junction depth of at least one other of said source region, drain region and buried layer regions.

6. The semiconductor device of claim 1 , further comprising a resistive change element connected to one of said source region or said drain region.