FinFET LDMOS devices with improved reliability
A finFET LDMOS semiconductor device includes a first well disposed adjacent to a second well on a substrate and a third well disposed on the substrate, wherein the second well is disposed between the first well and the third well. Additionally, the finFET LDMOS semiconductor device includes a source disposed on the first well, a fin at least partially disposed on the first well and adjacent to the source, a drain disposed on the third well, a shallow trench isolation (STI) disposed at least partially in the third well, and a STI protection structure disposed on the substrate between the second well and the third well and along a side of the STI that is closest to the source, wherein the STI protection structure is configured to discourage a drain to source current from flowing along the side of the STI that is closest to the source.
1. A finFET LDMOS semiconductor device, comprising:
a first well disposed adjacent to a second well on a substrate;
a third well disposed on the substrate, wherein the second well is disposed between the first well and the third well;
a source disposed on the first well;
a fin at least partially disposed on the first well and adjacent to the source;
a drain disposed on the third well;
a shallow trench isolation (STI) disposed at least partially in the third well; and
a STI protection structure disposed on the substrate, the STI protection structure being further disposed between the second well and the third well and along a side wall of the STI that faces the second well, wherein the STI protection structure is configured to discourage a drain to source current from flowing along the side wall of the STI that faces the second well.
2. The finFET LDMOS semiconductor device of claim 1 , wherein the first well comprises a P-doped material.
3. The finFET LDMOS semiconductor device of claim 2 , wherein each of the second well and third well comprises an N-doped material.
4. The finFET LDMOS semiconductor device of claim 1 , wherein the second well is positioned on a side of the STI closest to the source and the third well is positioned on an opposite side of the STI.
5. The finFET LDMOS semiconductor device of claim 1 , wherein the STI protection structure is a same material as the substrate.
6. The finFET LDMOS semiconductor device of claim 1 , wherein the STI protection structure comprises a P-doped material.
7. The finFET LDMOS semiconductor device of claim 1 , wherein the substrate comprises a deep N-well and the second well and the third well being positioned on the deep N-well.
8. The finFET LDMOS semiconductor device of claim 7 , wherein the substrate comprises the deep N-well, the second well, the third well and at least a portion of the first well being positioned on the deep N-well.
9. The finFET LDMOS semiconductor device of claim 1 , wherein a total height of the fin is 100-150 nanometers.
10. The finFET LDMOS semiconductor device of claim 1 , wherein a length of the STI is 50-100 nanometers.
11. A finFET LDMOS semiconductor device, comprising:
a first well disposed adjacent to a second well on a substrate;
a third well disposed on the substrate, wherein the second well is disposed between the first well and the third well;
a source disposed on the first well;
a fin at least partially disposed on the first well and adjacent to the source;
a pseudo drain at least partially disposed on the second well;
a drain disposed on the third well;
a shallow trench isolation (STI) disposed at least partially in the third well; and
a STI protection structure disposed on the substrate, the STI protection structure being further disposed between the second well and the third well and along a side wall of the STI that faces the second well, wherein the STI protection structure is configured to discourage a drain to source current from flowing along the side wall of the STI that faces the second well.
12. The finFET LDMOS semiconductor device of claim 11 , wherein the first well comprises a P-doped material.
13. The finFET LDMOS semiconductor device of claim 12 , each of the second well and third well comprises an N-doped material.
14. The finFET LDMOS semiconductor device of claim 11 , wherein the second well is positioned on a side of the STI closest to the source and the third well is positioned on an opposite side of the STI.
15. The finFET LDMOS semiconductor device of claim 11 , wherein the STI protection structure comprises a P-doped material.
16. The finFET LDMOS semiconductor device of claim 11 , wherein the substrate comprises a deep N-well and the second well and the third well being positioned on the deep N-well.
17. The finFET LDMOS semiconductor device of claim 16 , wherein the substrate comprises the deep N-well and the second well and the third well and at least a portion of the first well being positioned on the deep N-well.
18. The finFET LDMOS semiconductor device of claim 11 , wherein a total height of the fin is 100-150 nanometers.
19. The finFET LDMOS semiconductor device of claim 11 , wherein a length of the STI is 50-100 nanometers.