Loading a serial presence detect table according to jumper settings
Technologies are disclosed herein for configuring a system memory of a computer system by determining which, of a plurality, of serial presence detect (SPD) tables to utilize, based at least in part on settings of one or more GPIO pins. The computer system may be available with variations of the configuration of system memory. The SPD tables corresponding to each of the different configurations of the system memory may be stored on the computer system, such as on an NVRAM of the computer system. After identifying the appropriate SPD table, a processor may load the SPD table to a memory reference code of the computer system. In some cases, the state GPIO pins indicating the system memory configuration is set at the time of manufacture of the computer system.
1. A computer implemented method, comprising: accessing, by one or more processors, one or more general purpose input/output (GPIO) pins, wherein the one or more GPIO pins comprise first GPIO pins, second GPIO pins, and third GPIO pins, wherein the first GPIO pins correspond to a channel type and the second GPIO pins and the third GPIO pins indicate a memory size;
determining, by the one or more processors, a state of the one or more GPIO pins; determining, by the one or more processors, a serial presence detect (SPD) table using at least the state of the one or more GPIO pins, the SPD table determined by accessing a correspondence table indicating that the SPD table corresponds to the state of the one or more GPIO pins, wherein the correspondence table is stored in a non-volatile random access memory (NVRAM); loading, by the one or more processors, the SPD table to a memory reference code structure.
2. The method of claim 1 , wherein the state of the one or more GPIO pins indicate a size of a system memory.
3. The method of claim 1 , wherein the state of the one or more GPIO pins indicate a channel type of a system memory.
4. The method of claim 1 , wherein the SPD table is a first SPD table and a plurality of SPD tables are stored on the nonvolatile random access memory (NVRAM), the plurality of SPD tables comprising the first SPD table.
5. The method of claim 1 , wherein the one or more GPIO pins are set during manufacture of a computer.
6. An apparatus, comprising: at least one processor; one or more general purpose input/output (GPIO) pins; and one or more computer-readable storage media having instructions stored thereupon that are executable by the at least one processor and which, when executed by the at least one processor, cause the apparatus to: access the one or more GPIO pins, wherein the one or more GPIO pins comprise first GPIO pins, second GPIO pins, and third GPIO pins, wherein the first GPIO pins correspond to a channel type and the second GPIO pins and the third GPIO pins indicate a memory size; determine a state of the one or more GPIO pins; obtain, using at least the state of the one or more GPIO pins, a serial presence detect (SPD) table corresponding to the system memory identified by the state of the one or more GPIO pins, the SPD table obtained by accessing a correspondence table that indicates that the SPD table corresponds to the state of the one or more GPIO pins, wherein the correspondence table is stored in a non-volatile random access memory (NVRAM); and load the SPD table to a memory reference code structure.
7. The apparatus of claim 6 , wherein the state of the one or more GPIO pins indicate a size of a system memory.
8. The apparatus of claim 6 , wherein the state of the one or more GPIO pins indicate a channel type of a system memory.
9. The apparatus of claim 6 , wherein the SPD table is a first SPD table and a plurality of SPD tables are stored on the nonvolatile random access memory (NVRAM), the plurality of SPD tables comprising the first SPD table.
10. The apparatus of claim 6 , wherein the one or more GPIO pins are set during manufacture of the apparatus.
11. A non-transitory computer-readable storage medium having instructions stored thereupon which, when executed by a processor. cause the processor to perform operations comprising: accessing one or more general purpose input/output (GPIO) pins, wherein the one or more GPIO pins comprise first GPIO pins, second GPIO pins, and third GPIO pins, wherein the first GPIO pins correspond to a channel type and the second GPIO pins and the third GPIO pins indicate a memory size;
determining a state of the one or more GPIO pins; accessing, based at least in part on the state of the one or more GPIO pins, a serial presence detect (SPD) table corresponding to a system memory identified by the state of the one or more GPIO pins, the accessing comprising accessing a correspondence table that indicates that the SPD table corresponds to the state of the one or more GPIO pins, wherein the correspondence table is stored in a non-volatile random access memory (NVRAM); and loading the SPD table to a memory reference code structure.
12. The non-transitory computer-readable storage medium of claim 11 , wherein the state of the one or more GPIO pins indicate a size of a system memory.
13. The non-transitory computer-readable storage medium of claim 11 , wherein the state of the one or more GPIO pins indicate a channel type of a system memory.
14. The non-transitory computer-readable storage medium of claim 11 , wherein the SPD table is a first SPD table and a plurality of SPD tables are stored on the nonvolatile random access memory (NVRAM), the plurality of SPD tables comprising the first SPD table.