Systems and methods for resetting one or more system components in response to a watchdog timer (WDT) event
View Patent ↗Embodiments of information handling systems and methods are provided herein for resetting one or more system components in response to a watchdog timer (WDT) event. More specifically, the present disclosure provides information handling systems and methods for handling WDT events that occur within information handling systems comprising enhanced Serial Peripheral Interface (eSPI) master and slave devices.
1. An information handling system, comprising:
a platform controller hub (PCH);
an embedded controller (EC) having a plurality of input/output (I/O) pins, which are coupled via an enhanced Serial Peripheral Interface (eSPI) bus to the PCH;
a watch dog timer (WDT) configured to expire after a period of time;
wherein the plurality of I/O pins are tri-stated in an undefined logic state upon expiration of the WDT; and
wherein upon expiration of the WDT, the EC is configured to supply a first signal via a first one of the I/O pins and a second signal via a second one of the I/O pins to the PCH, wherein the first and second signals supplied to the PCH are pulled down from the undefined logic state to a logic low state while an operating voltage is supplied to the PCH at a desired voltage level.
2. The information handling system as recited in claim 1 , further comprising a first resistor and a second resistor, wherein:
the first resistor is coupled between the first one of the I/O pins and ground to pull the first signal down from the undefined logic state to the logic low state; and
the second resistor is coupled between the second one of the I/O pins and ground to pull the second signal down from the undefined logic state to the logic low state.
3. The information handling system as recited in claim 1 , further comprising a power controller coupled to receive a third signal from the PCH, control the operating voltage supplied to the PCH based on the third signal, and supply a fourth signal to the EC in a logic high state when the operating voltage is at the desired voltage level.
4. The information handling system as recited in claim 3 , wherein after the first and second signals are pulled down to the logic low state, the operating voltage supplied to the PCH is reduced below the desired voltage level to reset the PCH, and the power controller is configured to transition the fourth signal to the logic low state to indicate that the operating voltage is insufficient.
5. The information handling system as recited in claim 4 , wherein after supplying the first signal to the PCH in the logic low state for a predetermined amount of time, the EC is configured to transition the first signal from the logic low state to a logic high state.
6. The information handling system as recited in claim 5 , wherein after the first signal transitions to the logic high state, the operating voltage supplied to the PCH is increased to the desired voltage level, and the power controller is configured to transition the fourth signal to the logic high state to indicate that the operating voltage is at the desired voltage level.
7. The information handling system as recited in claim 6 , wherein after the power controller transitions the fourth signal to the logic high state, the EC is configured to transition the second signal from the logic low state to the logic high state to release the PCH from reset.
8. A method for resetting a platform controller hub (PCH) in response to a watchdog timer (WDT) event that occurs within an embedded controller (EC) having a plurality of input/output (I/O) pins, which are coupled to the PCH via an enhanced Serial Peripheral Interface (eSPI) bus, the method comprising:
tri-stating the plurality of input/output (I/O) pins in an undefined logic state in response to a WDT event;
supplying, from the EC, a first signal via a first one of the I/O pins and a second signal via a second one of the I/O pins to the PCH; and
pulling, via a pair of resistors coupled to the first and second I/O pins, the first and second signals supplied to the PCH down from the undefined logic state to a logic low state while an operating voltage is supplied to the PCH at a desired voltage level.
9. The method as recited in claim 8 , wherein after the step of pulling the first and second signals supplied to the PCH down from the undefined logic state to the logic low state, the method further comprises:
receiving a third signal from the PCH, the third signal received by a power controller coupled between the PCH and the EC;
reducing the operating voltage supplied to the PCH to a voltage level below the desired voltage level to reset the PCH; and (bringing the voltage down is not really what resets the PCH, the PCH is reset by the RSMRST# control signal)
providing, via the power controller, a fourth signal to the EC in the logic low state to indicate that the operating voltage supplied to the PCH is insufficient.
10. The method as recited in claim 9 , wherein after the first signal is supplied in the logic low state for a predetermined amount of time, the method further comprises executing firmware within the EC to transition the first signal from the logic low state to a logic high state.
11. The method system as recited in claim 10 , wherein after the first signal transitions to the logic high state, the method further comprises:
increasing the operating voltage supplied to the PCH to the desired voltage level; and
transitioning the fourth signal to the logic high state to indicate that the operating voltage supplied to the PCH is at the desired voltage level.
12. The method as recited in claim 11 , wherein after the fourth signal transitions to the logic high state, the method further comprises executing firmware within the EC to transition the second signal from the logic low state to the logic high state to release the PCH from reset.
13. An information handling system, comprising:
a platform controller hub (PCH);
a shared memory device coupled to the PCH via a Serial Peripheral Interface (SPI) bus;
an embedded controller (EC) coupled to the PCH via an enhanced Serial Peripheral Interface (eSPI) bus, wherein the embedded controller comprises:
a plurality of input/output (I/O) pins coupled to the PCH via the eSPI bus;
a processing device configured to execute a first set of program instructions to fetch a second set of program instructions from the shared memory device, and further configured to execute the second set of program instructions; and
a watch dog timer (WDT) configured to expire after a predetermined time period if a problem occurs during execution of the second set of program instructions;
wherein if the WDT expires, the EC is configured to supply a first signal via a first one of the I/O pins and a second signal via a second one of the I/O pins to the PCH, wherein the first and second signals are pulled down from an undefined logic state to a logic low state while an operating voltage is supplied to the PCH at a desired voltage level.
14. The information handling system as recited in claim 13 , wherein the EC further comprises:
read only memory (ROM) configured for storing the first set of program instructions; and
random access memory (RAM) configured for storing the second set of program instructions after the second set of program instructions is fetched from the shared memory device.
15. The information handling system as recited in claim 13 , further comprising a first resistor and a second resistor, wherein:
the first resistor is coupled between the first one of the I/O pins and ground to pull the first signal down from the undefined logic state to the logic low state; and
the second resistor is coupled between the second one of the I/O pins and ground to pull the second signal down from the undefined logic state to the logic low state.
16. The information handling system as recited in claim 13 , further comprising a power controller coupled to receive a third signal from the PCH, control the operating voltage supplied to the PCH based on the third signal, and supply a fourth signal to the EC in a logic high state when the operating voltage is at the desired voltage level.
17. The information handling system as recited in claim 16 , wherein after the first and second signals are pulled down to the logic low state, the operating voltage supplied to the PCH is reduced below the desired voltage level to reset the PCH, and the power controller is configured to transition the fourth signal to the logic low state to indicate that the operating voltage is insufficient, (again lowering the operating voltage is not the main method to reset the PCH, lowering the voltage is a power savings event to keep the PCH in a lower power state).
18. The information handling system as recited in claim 17 , wherein after the first signal is supplied to the PCH in the logic low state for a first predetermined amount of time, the EC is configured to transition the first signal from the logic low state to a logic high state.
19. The information handling system as recited in claim 18 , wherein after the first signal transitions to the logic high state, the operating voltage supplied to the PCH is increased to the desired voltage level, and the power controller is configured to transition the fourth signal to the logic high state to indicate that the operating voltage supplied to the PCH is at the desired voltage level.
20. The information handling system as recited in claim 19 , wherein after the power controller transitions the fourth signal to the logic high state, the EC is configured to transition the second signal from the logic low state to the logic high state to release the PCH from reset.