System and method for post-package repair across DRAM banks and bank groups
A dynamic random access memory (DRAM) device includes a plurality of bank groups of first storage cells, each bank group arranged as a plurality of banks, each bank arranged as a plurality of rows, and each row including a plurality of dynamic storage cells. The DRAM device further includes a post-package repair (PPR) storage array arranged as a plurality of entries, wherein the DRAM device is configured to map a first row failure in a first bank group to a first entry of the PPR storage array, and to map a second row failure in a second bank group to a second entry of the PPR storage array.
1. A dynamic random access memory (DRAM) device, comprising:
a plurality of bank groups of first storage cells, each bank group arranged as a plurality of banks, each bank arranged as a plurality of rows, and each row including a plurality of dynamic storage cells; and
a post-package repair (PPR) storage array arranged as a plurality of entries, each entry being associated with a PPR row, each PPR row including a plurality of dynamic storage cells, wherein the DRAM device is configured to map a first row failure from a first row in a first bank group to a first entry of the PPR storage array, to store first row data associated with the first row in a first PPR row associated with the first entry, to map a second row failure from a second row in a second bank group to a second entry of the PPR storage array, and to store second row data associated with the second row in a second PPR row associated with the second entry.
2. The DRAM device of claim 1 , wherein the first entry includes a map field.
3. The DRAM device of claim 2 , wherein the map field identifies the first bank group, a first bank within the first bank group, and a first row within the first bank, the first row including the first row failure.
4. The DRAM device of claim 3 , wherein the map field is fused to include the first bank group, the first bank, and the first row.
5. The DRAM device of claim 3 , wherein the first entry further includes a row data field configured to store data mapped from the first row.
6. The DRAM device of claim 2 , wherein the map field is cleared when the DRAM device is reset.
7. The DRAM device of claim 1 , wherein the first entry includes a valid field configured to indicate that the first row failure is mapped to the first entry.
8. The DRAM device of claim 1 , wherein the PPR storage array includes second storage cells.
9. The DRAM device of claim 8 , wherein the first storage cells comprise dynamic storage cells, and the second storage cells comprise static storage cells.
10. The DRAM device of claim 8 , wherein the first and second storage cells comprise dynamic storage cells.
11. A method, comprising:
arranging a dynamic random access memory (DRAM) device as a plurality of bank groups of first storage cells, each bank group arranged as a plurality of banks, each bank arranged as a plurality of rows, and each row including a plurality of dynamic storage cells;
arranging a post-package repair (PPR) storage array of the DRAM device as a plurality of entries, each entry being associated with a PPR row, each PPR row including a plurality of dynamic storage cells;
mapping, by the DRAM device, a first row failure in a first bank group to a first entry of the PPR storage array;
storing first row data associated with the first row in a first PPR row associated with the first entry;
mapping, by the DRAM device, a second row failure in a second bank group to a second entry of the PPR storage array; and
storing second row data associated with the second row in a second PPR row associated with the second entry.
12. The method of claim 11 , wherein the first entry includes a map field.
13. The method of claim 12 , wherein the map field identifies the first bank group, a first bank within the first bank group, and a first row within the first bank, the first row including the first row failure.
14. The method of claim 13 , further comprising:
fusing the map field to include the first bank group, the first bank, and the first row.
15. The method of claim 13 , wherein the first entry further includes a row data field, the method further comprising:
configuring the row data field to store data mapped from the first row.
16. The method of claim 12 , further comprising:
clearing the map field when the DRAM device is reset.
17. The method of claim 11 , wherein the first entry includes a valid field, the method further comprising:
configuring the valid field to indicate that the first row failure is mapped to the first entry.
18. The method of claim 11 , wherein the PPR storage array includes second storage cells, and wherein the first storage cells comprise dynamic storage cells, and the second storage cells comprise static storage cells.
19. The method of claim 11 , wherein the PPR storage array includes second storage cells, and wherein the first and second storage cells comprise dynamic storage cells.
20. A dynamic random access memory (DRAM) device, comprising:
a plurality of bank groups of first storage cells, each bank group arranged as a plurality of banks, each bank arranged as a plurality of rows, each row arranged as a plurality of chunks, and each chunk including a plurality of dynamic storage cells; and
a post-package repair (PPR) storage array arranged as a plurality of entries, each entry being associated with a PPR chunk, each PPR chunk including a plurality of dynamic storage cells, wherein the DRAM device is configured to map a first chunk failure from a first chunk in a first bank group to a first entry of the PPR storage array, to store first chunk data associated with the first chunk in a first PPR chunk associated with the first entry, to map a second chunk failure from a second chunk in a second bank group to a second entry of the PPR storage array, and to store second chunk data associated with the second chunk in a second PPR chunk associated with the second entry.