IP Library Granted Patent US 10,678,467
Granted Patent B2
US 10,678,467 · App. 15/727,173 · Granted Jun 9, 2020

Systems and methods for selective save operations in a persistent memory

Inventors: Vadhiraj Sankaranarayanan (Austin, TX); Krishna Pradyumna Kakarla (Round Rock, TX); Balaji Bapu Gururaja Rao (Austin, TX); Elie Antoun Jreij (Pflugerville, TX)
Assignee: Dell Products L.P.
G06F3/065G06F3/0619G06F3/0647G06F3/0685G06F12/02G06F3/0631G06F12/10G06F2212/65G06F2212/7203G06F2212/7208
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,678,467
App. No.
15/727,173
Granted
Jun 9, 2020
Kind
B2
Abstract

In accordance with embodiments of the present disclosure, an information handling system may include a processor and a persistent memory system communicatively coupled to the processor, the persistent memory system comprising one or more persistent memory modules and a plurality of targeted save registers, each targeted save register associated with a respective portion of the persistent memory system, and each targeted save register having a value indicative of how save operations from volatile memory to non-volatile memory of the persistent memory system are to be performed with respect to the respective portion of the persistent memory system.

Claims (21)

1. An information handling system comprising:

a processor; and

a persistent memory system communicatively coupled to the processor, the persistent memory system comprising one or more persistent memory modules and a plurality of targeted save registers, each targeted save register associated with a respective portion of the persistent memory system, and each targeted save register having a value indicative of a data criticality level for data stored in the respective portion, the data criticality level being usable to determine whether or not save operations from volatile memory to non-volatile memory of the persistent memory system are to be performed with respect to the respective portion of the persistent memory system;

wherein each of the respective portions comprises a respective Joint Electron Device Engineering Council (JEDEC) rank of the persistent memory system.

2. The information handling system of claim 1 , wherein the value of each targeted save register sets forth, with respect to the respective portion of the persistent memory system associated with the targeted save register, a second portion of the persistent memory system to which data stored in volatile memory of the respective portion of the persistent memory system is duplicated in response to a condition for performing a save operation.

3. The information handling system of claim 1 , wherein the processor is configured to, alone or in combination with a memory controller of the persistent memory system, set values of the targeted save registers for usage and provisioning of the persistent memory system by the processor.

4. The information handling system of claim 3 , wherein the processor is further configured to set values of the targeted save registers based on capacity of a battery for powering a save operation, and/or health of computer-readable media making up the persistent memory system.

5. A method comprising, in a persistent memory system comprising one or more persistent memory modules and a plurality of targeted save registers associated with respective portions of the persistent memory system:

storing a respective value in each of the plurality of targeted save registers; and

performing a save operation of the persistent memory system based on the respective values, wherein each respective value is indicative of a data criticality level for data stored in the respective portion, the data criticality level being usable to determine whether or not save operations from volatile memory to non-volatile memory of the persistent memory system are to be performed with respect to the respective portion of the persistent memory system;

wherein each of the respective portions comprises a respective Joint Electron Device Engineering Council (JEDEC) rank of the persistent memory system.

6. The method of claim 5 , wherein the value of each targeted save register sets forth, with respect to the respective portion of the persistent memory system associated with the targeted save register, a second portion of the persistent memory system to which data stored in volatile memory of the respective portion of the persistent memory system is duplicated in response to a condition for performing a save operation.

7. The method of claim 5 , wherein setting the values comprises setting values of the targeted save registers for usage and provisioning of the persistent memory system by a processor communicatively coupled to the persistent memory system.

8. The method of claim 7 , further comprising setting values of the targeted save registers based on capacity of a battery for powering a save operation, and/or health of computer-readable media making up the persistent memory system.

9. A persistent memory system comprising:

one or more persistent memory modules; and

a plurality of targeted save registers, each targeted save register associated with a respective portion of the persistent memory system, and each targeted save register having a value indicative of a data criticality level for data stored in the respective portion, the data criticality level being usable to determine whether or not save operations from volatile memory to non-volatile memory of the persistent memory system are to be performed with respect to the respective portion of the persistent memory systems;

wherein each of the respective portions comprises a respective Joint Electron Device Engineering Council (JEDEC) rank of the persistent memory system.

10. The persistent memory system of claim 9 , wherein the value of each targeted save register sets forth, with respect to the respective portion of the persistent memory system associated with the targeted save register, a second portion of the persistent memory system to which data stored in volatile memory of the respective portion of the persistent memory system is duplicated in response to a condition for performing a save operation.

11. The persistent memory system of claim 9 , wherein values of the targeted save registers are set by a processor communicatively coupled to the persistent memory system, alone or in combination with a memory controller of the persistent memory system, for usage and provisioning of the persistent memory system by the processor.

12. The persistent memory system of claim 11 , wherein the processor is further configured to set values of the targeted save registers based on capacity of a battery for powering a save operation, and/or health of computer-readable media making up the persistent memory system.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (044535/0109) Recorded May 20, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO WYSE TECHNOLOGY L.L.C.)
Reel/Frame 060753/0414 →
RELEASE OF SECURITY INTEREST AT REEL 044535 FRAME 0001 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; WYSE TECHNOLOGY L.L.C.
Reel/Frame 058298/0475 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Nov 29, 2017
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 044535/0109 →
PATENT SECURITY AGREEMENT (CREDIT) Recorded Nov 29, 2017
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; WYSE TECHNOLOGY L.L.C.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 044535/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 12, 2017
From: SANKARANARAYANAN, VADHIRAJ; KAKARLA, KRISHNA PRADYUMNA; RAO, BALAJI BAPU GURURAJA; JREIJ, ELIE ANTOUN
To: DELL PRODUCTS L.P.
Reel/Frame 043852/0587 →