Systems and methods for granular non-volatile memory health visibility to a host
In accordance with embodiments of the present disclosure, an information handling system may include a processor and a memory system communicatively coupled to the processor. The memory system may include one or more persistent memory modules, each of the one or more persistent memory modules comprising a volatile memory and a non-volatile memory and one or more health registers accessible to a host system executing on the processor, the health registers storing health information indicating, for each of a plurality of ranks of the volatile memory, whether the memory system can reliably perform a save operation to a portion of non-volatile memory mapped to volatile memory of the rank.
1. An information handling system comprising:
a processor; and
a memory system communicatively coupled to the processor, the memory system comprising:
one or more persistent memory modules, each of the one or more persistent memory modules comprising a volatile memory and a non-volatile memory; and
one or more health registers accessible to a host system executing on the processor, the one or more health registers configured to store health information indicating, separately for each of a plurality of ranks of the volatile memory and at a rank-level granularity, whether the memory system can reliably perform a save operation to a portion of non-volatile memory mapped to volatile memory of the rank;
wherein each rank comprises a respective Joint Electron Device Engineering Council (JEDEC) rank of the volatile memory.
2. The information handling system of claim 1 , wherein the health information includes information regarding correctable restore errors.
3. The information handling system of claim 2 , wherein the health information includes a severity for each correctable restore error.
4. The information handling system of claim 1 , wherein the health information includes information regarding the usage of the volatile memory or the non-volatile memory within each rank.
5. The information handling system of claim 1 , wherein the health information includes runtime updates regarding memory media health based on diagnostic tests.
6. The information handling system of claim 1 , wherein the host system executing on the processor is further configured to:
read rank-level health information from the one or more health registers; and
allocate data to physical addresses of the memory system based on the rank-level health information.
7. The information handling system of claim 6 , wherein allocating data to physical addresses comprises mapping of virtual memory addresses to physical memory addresses based on the health information.
8. A method comprising, in a memory system comprising one or more persistent memory modules, each of the one or more persistent memory modules comprising a volatile memory and a non-volatile memory:
storing health information in one or more health registers of a memory system, the health information indicating, separately for each of a plurality of ranks of the volatile memory and at a rank-level granularity, whether the memory system can reliably perform a save operation to a portion of non-volatile memory mapped to volatile memory of the rank, such that the health information is accessible to a host system executing on a processor communicatively coupled to the memory system;
wherein each rank comprises a respective Joint Electron Device Engineering Council (JEDEC) rank of the volatile memory.
9. The method of claim 8 , wherein the health information includes information regarding correctable restore errors.
10. The method of claim 9 , wherein the health information includes a severity for each correctable restore error.
11. The method of claim 8 , wherein the health information includes information regarding the usage of the volatile memory or the non-volatile memory within each rank.
12. The method of claim 8 , wherein the health information includes runtime updates regarding memory media health based on diagnostic tests.
13. The method of claim 8 , further comprising, by the host system executing on the processor communicatively coupled to the memory system:
reading rank-level health information from the one or more health registers; and
allocating data to physical addresses of the memory system based on the rank-level health information.
14. The method of claim 13 , wherein allocating data to physical addresses comprises mapping of virtual memory addresses to physical memory addresses based on the health information.
15. A memory system comprising:
one or more persistent memory modules, each of the one or more persistent memory modules comprising a volatile memory and a non-volatile memory; and
one or more health registers accessible to a host system, the one or more health registers configured to store health information indicating, separately for each of a plurality of ranks of the volatile memory and at a rank-level granularity, whether the memory system can reliably perform a save operation to a portion of non-volatile memory mapped to volatile memory of the rank;
wherein each rank comprises a respective Joint Electron Device Engineering Council (JEDEC) rank of the volatile memory.
16. The memory system of claim 15 , wherein the health information includes information regarding correctable restore errors.
17. The memory system of claim 16 , wherein the health information includes a severity for each correctable restore error.
18. The memory system of claim 15 , wherein the health information includes information regarding the usage of the volatile memory or the non-volatile memory within the rank.
19. The memory system of claim 15 , wherein the health information includes runtime updates regarding memory media health based on diagnostic tests.
20. The memory system of claim 15 , wherein the host system is further configured to:
read rank-level health information from the one or more health registers; and
allocate data to physical addresses of the memory system based on the rank-level health information.