Coordinated event sequencing
View Patent ↗Methods and systems of synchronizing events using a plurality of sequencing controllers are provided. For each sequencing controller, a serial communication bus (SCB) is monitored for a first reference level. Upon identifying that the SCB is at the first reference level for a predetermined period, a bit sequence indicative of an event position is broadcast to be arbitrated on the SCB. The SCB is monitored for the arbitrated bit sequence. Upon determining that the arbitrated bit sequence corresponds to the bit sequence of the event position, an event corresponding to the event position is enabled.
1. A method of synchronizing events using a plurality of sequencing controllers, the method comprising:
monitoring, by one or more of the plurality of sequencing controllers, a serial communication bus (SCB) for a first reference level;
upon identifying that the SCB is at the first reference level for a predetermined period, broadcasting a bit sequence indicative of an event position to be arbitrated on the SCB;
monitoring the SCB for the bit sequence;
upon a given sequencing controller of the plurality of sequencing controllers determining that the monitored bit sequence corresponds to the bit sequence of the event position of the given sequencing controller, determining that the given sequencing controller wins a state arbitration and enabling an event corresponding to the event position, and
causing the given sequencing controller that wins the state arbitration to not participate in a subsequent event position arbitration.
2. The method of claim 1 , further comprising, upon determining that the enabled event has completed within a threshold time:
reporting the completion on the SCB; and
entering a standby mode until at least one of: (i) each of the plurality of sequencing controllers have had a turn to win an arbitration on the SCB, (ii) a sequencing direction change is detected, or (iii) a fault condition is identified.
3. The method of claim 2 , wherein the standby mode comprises at least one of:
(i) not broadcasting the bit sequence in subsequent arbitration cycles; or
(ii) broadcasting an event position higher than that of any other sequencing controller of the plurality of sequencing controllers.
4. The method of claim 1 , further comprising, upon enabling the event:
reporting the enablement on the SCB; and
staying in a standby mode for subsequent arbitration cycles until at least one of: (i) each of the plurality of sequencing controllers have had a turn to win an arbitration on the SCB, (ii) a sequencing direction change is detected, or (iii) a fault condition is identified.
5. The method of claim 1 , further comprising, upon determining a fault condition:
preventing a release of the SCB for subsequent arbitration cycles; and
reporting the fault condition on the SCB.
6. The method of claim 1 , further comprising, maintaining the SCB at a second reference level during the enabling of the event.
7. The method of claim 1 , wherein monitoring the SCB for the arbitrated bit sequence comprises:
reading a level of the SCB, for every broadcast bit of the event position;
storing the level of the SCB, for every broadcast bit of the event position, in a memory of the given sequencing controller, to create a present bus position; and
comparing the event position to the present bus position.
8. The method of claim 1 , wherein, during an arbitration, the second reference level is dominant over the first reference level on the SCB.
9. The method of claim 1 , wherein an event position of a down sequence of event synchronization is a bit-wise inverse of the event position of an up sequence.
10. The method of claim 1 , further comprising arbitrating a state bit prior to performing event position arbitration, wherein a loss of the state arbitration causes a sequencing controller that wins the state arbitration to not participate in the event position arbitration.
11. The method of claim 1 , wherein the SCB is a differential bus.
12. The method of claim 1 , wherein the SCB is a single wire bus.
13. The method of claim 1 , wherein the SCB comprises a serial data wire and a serial clock wire.
14. An apparatus for synchronizing an event using a sequencing controller, comprising:
means for monitoring a serial communication bus (SCB) for a first reference level;
means for upon identifying that the SCB is at the first reference level for a predetermined period, broadcasting a bit sequence indicative of an event position to be arbitrated on the SCB between any other sequencing controllers coupled to the SCB;
means for monitoring the SCB for the bit sequence;
means for upon determining that the monitored bit sequence corresponds to the bit sequence of the event position of the sequencing controller, determining that the sequencing controller wins a state arbitration and enabling an event corresponding to the event position; and
means for causing the sequencing controller that wins the state arbitration to not participate in a subsequent event position arbitration.
15. The apparatus of claim 14 , further comprising, upon determining that the enabled event has completed within a threshold time:
means for reporting the completion on the SCB; and
means for entering a standby mode until at least one of: (i) each of the plurality of sequencing controllers have had a turn to win an arbitration on the SCB, (ii) a sequencing direction change is detected, or (iii) a fault condition is identified.
16. The apparatus of claim 15 , wherein the standby mode comprises at least one of:
(i) means for not broadcasting the bit sequence in subsequent arbitration cycles; or
(ii) means for broadcasting an event position higher than that of any other sequencing controller of the plurality of sequencing controllers.
17. The apparatus of claim 14 , further comprising, upon enabling the event:
means for reporting the enablement on the SCB; and
means for staying in a standby mode for subsequent arbitration cycles until at least one of:
(i) each of the plurality of sequencing controllers have had a turn to win an arbitration on the SCB,
(ii) a sequencing direction change is detected, or (iii) a fault condition is identified.
18. The apparatus of claim 14 , further comprising, upon determining a fault condition:
means for preventing a release of the SCB for subsequent arbitration cycles; and
means for reporting the fault condition on the SCB.
19. The apparatus of claim 14 , further comprising, means for maintaining the SCB at a second reference level during the enabling of the event.
20. The apparatus of claim 14 , wherein means for monitoring the SCB for the bit sequence comprises:
means for reading a level of the SCB, for every broadcast bit of the event position;
means for storing the level of the SCB, for every broadcast bit of the event position, in a memory of the sequencing controller, to create a present bus position; and
means for comparing the event position to the present bus position.
21. The apparatus of claim 14 , wherein, during an arbitration, the second reference level is dominant over the first reference level on the SCB.
22. The apparatus of claim 14 , wherein an event position of a down sequence of the event synchronization is a bit-wise inverse of the event position of an up sequence.
23. The apparatus of claim 14 , further comprising means for arbitrating a state bit prior to performing event position arbitration, wherein a loss of the state arbitration causes a given sequencing controller that wins the state arbitration to not participate in the event position arbitration.
24. The apparatus of claim 14 , wherein the SCB is a differential bus.
25. The apparatus of claim 14 , wherein the SCB is a single wire bus.
26. The apparatus of claim 14 , wherein the SCB comprises a serial data wire and a serial clock wire.
27. A sequencing controller comprising:
a bidirectional terminal coupled to a serial communication bus (SCB);
and
a control logic unit having a first input coupled to an output of the bidirectional terminal and an enable port operative to control a device,
wherein the control logic unit is configured to:
enable the device upon winning an arbitration with other sequencing controllers coupled to the SCB, upon broadcasting a bit sequence indicative of an event position on the SCB; and
prevent the sequencing controller that wins the arbitration participating in a subsequent arbitration.
28. The sequencing controller of claim 27 , wherein the control logic unit is further configured to, upon determining that the enabled event has completed within a threshold time:
report the completion on the SCB; and
enter a standby mode until at least one of: (i) each of the plurality of sequencing controllers have had a turn to win an arbitration on the SCB, (ii) a sequencing direction change is detected, or (iii) a fault condition is identified.
29. The sequencing controller of claim 27 , wherein the SCB is a differential bus.
30. The sequencing controller of claim 27 , wherein the SCB is a single wire bus.
31. The sequencing controller of claim 27 , wherein the SCB comprises a serial data wire and a serial clock wire.
32. The sequencing controller of claim 27 , wherein the device is a power supply, and wherein an event position of a down sequence of event synchronization is a bit-wise inverse of the event position of an up sequence.