IP Library Granted Patent US 10,496,444
Granted Patent B2
US 10,496,444 · App. 15/743,630 · Granted Dec 3, 2019

Computer and control method for computer

Inventors: Sachie Tajima (Tokyo, JP); Masakuni Agetsuma (Tokyo, JP); Takanobu Suzuki (Tokyo, JP); Akihiko Araki (Tokyo, JP)
Assignee: HITACHI, LTD.
G06F9/5016G06F9/5027G06F12/0646G06F13/10G06F13/28G06F2212/1048G06F2212/604G06F2213/2806
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Quick Facts
Patent No.
US 10,496,444
App. No.
15/743,630
Granted
Dec 3, 2019
Kind
B2
Abstract

By assigning a physically continuous memory area to a virtual storage apparatus operated on an OS, the performance of the virtual storage apparatus is secured. A processor operates an OS, and the processor executes a plurality of processes on the OS. The plurality of processes includes a first virtual storage apparatus. The first virtual storage apparatus executes an I/O process, and includes a cache for storing data that is subjected to the I/O process. The processor assigns a resource in a computer to the plurality of processes, and the processor creates area information that indicates physical addresses assigned to the processes in a memory. On the basis of the area information, the processor selects a continuous area, which is a physically continuous area from the memory and assigns the continuous area to the cache.

Claims (50)

1. A computer comprising:

a memory; and

a processor coupled to the memory,

a DMA controller which is coupled to the memory and the processor and is configured to perform transfer in accordance with a DMA transfer request from the processor;

an OS which is configured to be executed on the processor and execute a plurality of processes thereon,

wherein:

the plurality of processes include a first virtual storage apparatus which executes 10 processing to a storage device;

the DMA controller is configured to transfer data in which the first virtual storage apparatus performs 10;

the processor is configured to:

virtualize and allocate a first area of the memory to the plurality of processes including the first virtual

storage apparatus executing 10 processing, and

allocate a physically contiguous area to a second area of the memory as a cache where the first virtual storage apparatus and the DMA controller store and exchange data of the 10 ;

wherein

one of the plurality of processor is a second virtual storage apparatus,

the processor is configured to determine, when determination is made that the contiguous area having the specific size cannot be reserved, whether or not the size of an unallocated area of the second area is equal to or greater than the specific size, with this unallocated area having not been allocated to the first virtual storage apparatus, and

when determination is made that the size of the unallocated area is equal to or greater than the specific size, the processor is configured to:

change a specific area of the second area to an area in the unallocated area, with this specific area being allocated to the second virtual storage apparatus, thereby reserving the contiguous area having the specific size;

and

convert data in the specific area to a clean state, deallocate the specific area, and allocate an area in the unallocated area to the second virtual storage apparatus.

2. The computer according to claim 1 , wherein

upon receiving a setting request for configuring the size of the cache to a specific size, the processor is configured to determine whether or not the contiguous area having the specific size can be reserved on the basis of the area information, and

when determination is made that the contiguous area having the specific size can be reserved, the processor is configured to select the contiguous area having the specific size from the memory on the basis of the area information.

3. The computer according to claim 2 , wherein

the processor is configured to allocate computing power of the processor to the plurality of processes, and

the processor is configured to allocate a portion of the capacity of the memory to processes other than the cache from among the plurality of processes.

4. The computer according to claim 3 , wherein

the processor is configured to configure the first area, which is a portion of the memory, to the OS,

the processor is configured to allocate areas in the first area to the plurality of processes, and

the processor is configured to select the contiguous area from the second area in the memory, the second area differing from the first area.

5. The computer according to claim 3 , wherein

when determination is made that the contiguous area having the specific size cannot be reserved, the processor is configured to change, on the basis of the area information, an area allocated to a specific process among the plurality of processes, with this specific process being a process other than a virtual storage apparatus, to an area in the unallocated area of the memory, with this area having not been allocated to a process, whereby the contiguous area having the specific size is reserved.

6. The computer according to claim 5 , wherein

when determination is made that the contiguous area having the specific size cannot be reserved, the processor is configured to select, on the basis of the area information, the area allocated to the specific process as a migration source area, select, on the basis of the area information, an area in the unallocated area as a migration destination area, copy data in the migration source area to the migration destination area, and change the area allocated to the specific process from the migration source area to the migration destination area, whereby the contiguous area having the specific size is reserved.

7. The computer according to claim 6 , wherein

the processor is configured to pin down the contiguous area.

8. The computer according to claim 7 , wherein

the area information indicates physical addresses of areas in the memory which are allocated to respective processes.

9. A control method for a computer including a memory, a processor coupled to the memory, a DMA controller which is coupled to the memory and the processor and is configured to perform transfer in accordance with a DMA transfer request from the processor, and a OS which is configured to be executed on the processor and execute a plurality of processes thereon,

the control method comprising:

executing the plurality of processes of the OS involving a first virtual storage apparatus that executes 10 processing to a storage device;

transferring, from the DMA controller, data in which the first virtual storage apparatus performs 10,

virtualizing and allocating a first area of the memory to a plurality of processes including the first virtual storage apparatus and

allocating a physically contiguous area to a second area of the memory as a cache where the first virtual storage apparatus and the DMA controller store and exchange data of the IQ;

wherein

one of the plurality of processor is a second virtual storage apparatus,

the processor is configured to determine, when determination is made that the contiguous area having the specific size cannot be reserved, whether or not the size of an unallocated area of the second area is equal to or greater than the specific size, with this unallocated area having not been allocated to the first virtual storage apparatus, and

when determination is made that the size of the unallocated area is equal to or greater than the specific size, the processor is configured to:

change a specific area of the second area to an area in the unallocated area, with this specific area being allocated to the second virtual storage apparatus, thereby reserving the contiguous area having the specific size;

and

convert data in the specific area to a clean state, deallocate the specific area, and allocate an area in the unallocated area to the second virtual storage apparatus.

Assignments (2)
COMPANY SPLIT Recorded Aug 20, 2024
From: HITACHI, LTD.
To: HITACHI VANTARA, LTD.
Reel/Frame 069518/0761 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2018
From: TAJIMA, SACHIE; AGETSUMA, MASAKUNI; SUZUKI, TAKANOBU; ARAKI, AKIHIKO
To: HITACHI, LTD.
Reel/Frame 044590/0096 →
Continuity (1)
Related Publication 20180203733A1 · Jul 19, 2018