IP Library Granted Patent US 10,462,911
Granted Patent B2
US 10,462,911 · App. 15/758,217 · Granted Oct 29, 2019

High-current transmitting method utilizing printed circuit board

Inventors: Chang Hui Lee (Cheonan-Si, KR); Dong Hyun Kim (Sejong-Si, KR)
Assignee: LG CHEM, LTD.
H05K3/42H05K1/0265H05K1/09H05K1/115H05K3/0011H05K3/06H05K3/282H05K3/429H05K3/462H05K3/4623H05K3/4644H05K3/3447H05K2201/09572H05K2203/0502H05K2203/0548
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Quick Facts
Patent No.
US 10,462,911
App. No.
15/758,217
Granted
Oct 29, 2019
Kind
B2
Abstract

The present disclosure relates to a structure and a method for filling a via hole formed in a multilayer printed circuit board, and more particularly, to a structure and a method for filling a via hole formed in a multilayer printed circuit board, the structure and method enabling high-current transmission even in a narrow space in such a way that a via hole formed when a typical multilayer printed circuit board is manufactured is first filled with Cu and Ag plating, and the remaining vacant space is completely filled with a solder cream, thereby increasing the amount of conductors.

Claims (22)

1. A multilayer printed circuit board each layer of which is printed with a circuit pattern, the multilayer printed circuit board comprising via holes for connecting circuits of each layer, wherein each via hole is a through hole having a pair of open ends, and wherein each via hole comprises:

a plating layer formed on a side wall of the via hole, the plating layer including a Cu plating layer plated with Cu on the side wall of the via hole and an Au plating layer formed on the Cu plating layer; and

a solder cream on the Au plating layer and filled in a vacant surface of the via holes on which the plating layer is formed.

2. The multilayer printed circuit board of claim 1 , wherein the solder cream is reflowed.

3. The multilayer printed circuit board of claim 1 , wherein the Cu plating layer includes:

a first coating of Cu on the insides of the via holes formed by electroless copper plating; and

a second coating of Cu on the insides of the via holes formed by electrical copper plating.

4. A method for manufacturing a multilayer printed circuit board (MLB), comprising:

a copper foil forming step for plating a copper foil on an entire surface of a laminated plate to form a plurality of copper foil laminated plates;

an inner layer circuit printing step for coating the copper foil laminated plates formed in the copper foil laminated plate forming step with a photosensitive dry film and then with a master film on which a circuit is printed to form a circuit through light irradiation and development;

an etching step for removing unnecessary copper foils from surfaces of the copper foil laminated plates on which the printing of inner layer circuit is completed, to form a circuit;

a rest delaminating step for removing the dry film of a circuit portion to complete circuit formation;

a laminating process step for laminating and attaching each copper foil plate in which the circuit formation is completed;

a via hole processing step for forming via holes at positions connecting circuits located on layers different from each other in the laminated plates after the laminating process step;

a via hole plating step for plating the inside of the holes to be electrically connectable after processing the via holes in the via hole processing step;

a solder mask printing process step for applying a solder mask insulating ink to prevent the generation of a bridge of the soldering solder and the oxidation of exposed circuits when surface mounting for mounting components on an uppermost laminated substrate is performed;

a solder cream filling step for filling a vacant space of the via holes filled with plating when surface mounting for mounting components on the laminated plates is performed; and

a step for completely filling the holes filled with the solder cream in the solder cream filling step by performing a reflow of the solder cream.

5. The method of claim 4 , wherein the via hole plating step comprises firstly plating Cu and secondly plating Au.

6. The method of claim 4 , wherein the via hole plating step comprises:

first coating Cu on the insides of the via holes using electroless copper plating; and

second coating Cu on the insides of the via holes using electrical copper plating.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 4, 2021
From: LG CHEM, LTD.
To: LG ENERGY SOLUTION, LTD.
Reel/Frame 058295/0068 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 8, 2018
From: LEE, CHANG HUI; KIM, DONG HYUN
To: LG CHEM, LTD.
Reel/Frame 045144/0896 →
Priority Claims (1)
KR 10-2016-0070347 · Jun 7, 2016 · national
Continuity (1)
Related Publication 20180255648A1 · Sep 6, 2018