Optoelectronic semiconductor chip and method of producing an optoelectronic semiconductor chip
An optoelectronic semiconductor chip includes an active region arranged between a first semiconductor layer and a second semiconductor layer and generates or receives electromagnetic radiation, the first semiconductor layer electrically conductively connects to a first contact, the first contact is formed on a front side of the chip next to the active region, the second semiconductor layer electrically conductively connects to a second contact, the second contact is arranged on the front side of the chip next to the active region, and an electrically insulating separating layer that electrically insulates a rear side of the chip from the active region of the semiconductor chip, and an electrically insulating separating layer includes at least one first separating layer having at least one atomic layer or at least one molecular layer and is deposited by atomic layer deposition or molecular layer deposition.
1. An optoelectronic semiconductor chip comprising a carrier and a semiconductor body having a semiconductor layer sequence arranged on the carrier, and a front side of the chip and a rear side of the chip, wherein
the semiconductor layer sequence comprises an active region arranged between a first semiconductor layer and a second semiconductor layer and generates or receives electromagnetic radiation,
the first semiconductor layer electrically conductively connects to a first contact,
the first contact is formed on the front side of the chip next to the active region,
the second semiconductor layer electrically conductively connects to a second contact,
the second contact is arranged on the front side of the chip next to the active region, and
an electrically insulating separating layer that electrically insulates the rear side of the chip from the active region of the semiconductor chip, and the electrically insulating separating layer is formed of a first separating layer, a second separating layer and a third separating layer,
wherein the first separating layer, the second separating layer and the third separating layer are distinct layers, and
the first separating layer is formed by atomic layer deposition or molecular layer deposition.
2. The semiconductor chip according to claim 1 , wherein the electrically insulating separating layer is arranged on a front side of the carrier, on a rear side of the carrier or within the carrier.
3. The semiconductor chip according to claim 1 , wherein the first separating layer has an atomic layer and/or molecular layer having one or more layers.
4. The semiconductor chip according to claim 1 , wherein the first separating layer has at least one or more insulating oxide or nitride compounds or one or more material selected from the group consisting of Al x O y , SiO 2 , Ta x O y , TaN, TiO, SiN, AlN, TiN, ZrO 2 , HfO 2 , HfSiO 4 , ZrSiO 4 and HfSiON.
5. The semiconductor chip according claim 1 , wherein the electrically insulating separating layer is made of electrically insulating materials.
6. The semiconductor chip according to claim 1 , wherein the second separating layer has one or more layers deposited by gas phase deposition or sputtering methods.
7. The semiconductor chip according to claim 6 , wherein
the third separating layer has one or more layers deposited by a gas phase deposition or a sputtering method, and
the first separating layer is at least partially enclosed by the second and third separating layer.
8. The semiconductor chip according to claim 1 , wherein the second and/or the third separating layer has at least one or more insulating oxide or nitride compounds or one or more material selected from the group consisting of SiN x , Si—ON, SiO 2 , Al x O y , Ta x O y , TaN, TiO, SiN, AlN, TiN, ZrO 2 , HfO 2 , HfSiO 4 , ZrSiO 4 and HfSiON.
9. The semiconductor chip according to claim 1 , wherein the carrier comprises an electrically conductive material, semiconducting material, a molding material, a ceramic material and/or a high-resistance material.
10. The semiconductor chip according to claim 1 , wherein the first semiconductor layer is arranged on the side of the carrier facing away from the active region and the first semiconductor layer connects to the first contact via a first connection layer.
11. The semiconductor chip according to claim 1 , wherein the semiconductor body has at least one recess extending through the second semiconductor layer and through the active region, and the first connection layer is arranged at least partially in the recess and connects to the first semiconductor layer.
12. The semiconductor chip according to claim 1 ,
wherein the second semiconductor layer electrically conductively connects to the second contact via the second connection layer, and
the second connection layer is arranged on the side of the active region facing the carrier.
13. The semiconductor chip according to claim 1 , wherein
the electrically insulating separating layer is formed over the entire surface of a main surface of the carrier,
the second separating layer and the third separating layer are formed by gas phase deposition,
the first separating layer is arranged between the second separating layer and the third separating layer, and
the first separating layer is in direct contact with the second separating layer and the third separating layer.
14. A method of producing an optoelectronic semiconductor chip having a front side of the chip and an underside of the chip, comprising:
providing a semiconductor layer sequence having an active region arranged between a first semiconductor layer and a second semiconductor layer;
forming a first contact on the front side of the chip next to the active region, and forming an electrically conductive connection between the first semiconductor layer and the first contact,
forming a second contact on the front side of the chip next to the active region, and forming an electrically conductive connection between the second semiconductor layer and the second contact,
forming an electrically insulating separating layer by atomic layer coating or molecular layer coating that electrically insulates the rear side of the chip from the active region of the semiconductor chip, and
forming a composite of semiconductor layer sequence and carrier.
15. The method according to claim 14 , wherein
the electrically insulating separating layer is applied by combination of a first separating layer and at least one second separating layer,
the first separating layer is formed on the basis of atomic layer deposition or molecular layer deposition,
the second separating layer is formed on the basis of a gas phase deposition or on the basis of a sputtering method, and
the depositions of the first and second separating layer take place in immediate succession.
16. The method according to claim 14 , wherein the electrically insulating separating layer is applied by at least one of the following atomic layer coating and/or molecular layer coating methods:
atomic layer deposition,
atomic layer epitaxy,
atomic layer evaporation,
atomic layer growth,
molecular layer deposition, and
molecular layer epitaxy.
17. The method according to claim 14 , wherein
the electrically insulating separating layer is formed over the entire surface on a main surface of the carrier,
the electrically insulating separating layer is formed of a first separating layer, a second separating layer and a third separating layer,
wherein the first separating layer is arranged between the second separating layer and the third separating layer and the first separating layer is in contact with the second separating layer and the third separating layer,
the first separating layer is formed by atomic layer deposition or molecular layer deposition, and
the second separating layer and the third separating layer are formed by gas phase deposition.