Random clock generation

1. A random clock generator which comprising:

a clock signal input that receives a master clock signal composed of a series of regular and regularly spaced pulses,

a clock signal reduction circuit that receives the master clock signal and an integer N, and which provides an output signal corresponding to a train of N pulses every M clock pulses, where M is an integer greater than 1 and N is an integer greater than 1 and less than or equal to M,

a number generator, which provides a new number N to the clock signal reduction circuit, every P pulses of a master clock signal, with N and/or P produced randomly.

2. The random clock generator according to claim 1 , in which P is equal to M and N is produced randomly.

3. The random clock generator according to claim 1 , in which the number generator comprises a non-linear shift register and a random number generator, with this random number generator used to periodically reset the non-linear shift register.

4. The random clock generator according to claim 1 , in which N is between a minimum value (N min ) and a maximum value (N max ).

5. The random clock generator according to claim 4 , in which the number N is obtained as an output of an adder or an adder/subtractor that receives an average value (C) of N and a random correction value (R 0-2 ) to be added to or potentially subtracted from this average value.

6. The random clock generator according to claim 3 , in which the random correction value is provided by a non-linear shift register.

7. The random clock generator according to claim 4 , in which the random correction value is provided by a non-linear shift register.

8. The random clock generator according to claim 5 , in which the random correction value is provided by a non-linear shift register.