Apparatus and method for achieving glitch-free clock domain crossing signals
A computer implemented method includes identifying in an original circuit output signals that drive domain crossing logic separating a first clock domain from a second clock domain. A revised circuit is formed with a register attached to the domain crossing logic. The register receives an output signal and a synchronization signal that precludes the output signal from transitioning at selected clock cycle intervals.
1. A non-transitory computer readable storage medium, comprising executable instructions to:
identify in an original circuit output signals that drive domain crossing logic separating a first clock domain driven by a first clock from a second clock domain driven by a second clock wherein the first clock and second clock have different frequencies; and
form a revised circuit with a register attached to the domain crossing logic, wherein the register receives an output signal and a synchronization signal that precludes the output signal from transitioning at selected clock cycle intervals.
2. The non-transitory computer readable storage medium of claim 1 further comprising executable instructions to simultaneously apply test signals to the original circuit and the revised circuit and to evaluate output signals from the original circuit and the revised circuit for equivalency.
3. The non-transitory computer readable storage medium of claim 1 wherein the original circuit and the revised circuit are expressed in Register Transfer Level code.
4. A computer implemented method, comprising:
identifying in an original circuit output signals that drive domain crossing logic separating a first clock domain driven by a first clock from a second clock domain driven by a second clock wherein the first clock and second clock have different frequencies; and
forming a revised circuit with a register attached to the domain crossing logic, wherein the register receives an output signal and a synchronization signal that precludes the output signal from transitioning at selected clock cycle intervals.
5. The computer implemented method of claim 4 further comprising simultaneously applying test signals to the original circuit and the revised circuit and evaluating output signals from the original circuit and the revised circuit for equivalency.
6. The computer implemented method of claim 4 further comprising expressing the original circuit and the revised circuit in Register Transfer Level code.