IP Library Granted Patent US 10,199,977
Granted Patent B1
US 10,199,977 · App. 15/783,695 · Granted Feb 5, 2019

Electrical systems having interleaved DC interconnects

Inventors: Ali Mohammadpour (Torrance, CA); Andrew Love (Marina Del Ray, CA); Louis Pu (Torrance, CA); Mike Guidry (Redondo Beach, CA)
Assignee: Garrett Transportation I Inc.
H02P27/06H05K1/111H05K1/144H05K1/181H05K2201/042H05K2201/10015H05K2201/10166H05K2201/10272H05K2201/10522
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,199,977
App. No.
15/783,695
Granted
Feb 5, 2019
Kind
B1
Abstract

Electrical systems and devices with substrate interconnections having reduced parasitic inductance are provided. A first substrate includes one or more capacitors and plurality of connection interfaces, wherein a first subset of connection interfaces electrically connected to a first reference voltage are interleaved with a second subset of connection interfaces electrically connected to a different reference voltage. A second substrate includes a third subset of connection interfaces are electrically connected to a first terminal of a first switching element and the first subset of connection interfaces and a fourth subset of connection interfaces electrically connected to a second terminal of a second switching element and the second subset of connection interfaces, and the third subset and the fourth subset are also interleaved.

Claims (67)

1. An electrical system comprising:

a first substrate comprising one or more capacitors on a first side and a first plurality of connection interfaces on a second side opposite the first side, wherein:

a first subset of the first plurality of connection interfaces is electrically connected to a first reference voltage node;

a second subset of the first plurality of connection interfaces is electrically connected to a second reference voltage node different from the first reference voltage node; and

the first subset and the second subset are interleaved; and

a second substrate comprising a second plurality of connection interfaces, wherein:

a third subset of the second plurality of connection interfaces is electrically connected to a first terminal of a first switching element and coupled to the first subset of the first plurality of connection interfaces;

a fourth subset of the second plurality of connection interfaces is electrically connected to a second terminal of a second switching element and coupled to the second subset of the first plurality of connection interfaces; and

the third subset and the fourth subset are interleaved.

2. The electrical system of claim 1 , wherein:

the first subset and the third subset are in direct contact; and

the second subset and the fourth subset are in direct contact.

3. The electrical system of claim 1 , wherein individual connection interfaces of the second subset are interposed between individual connection interfaces of the first subset.

4. The electrical system of claim 1 , wherein connection interfaces of the first subset are spaced apart from neighboring connection interfaces of the first subset by an adjacent connection interface of the second subset.

5. The electrical system of claim 1 , wherein:

none of the connection interfaces of the first subset are adjacent to another of the connection interfaces of the first subset; and

none of the connection interfaces of the second subset are adjacent to another of the connection interfaces of the second subset.

6. The electrical system of claim 1 , wherein:

the first switching element comprises a first field effect transistor mounted on the second substrate; and

the second switching element comprises a second field effect transistor mounted on the second substrate.

7. The electrical system of claim 6 , wherein:

the first reference voltage node comprises a first bus bar on the first substrate; and

the second reference voltage node comprises a second bus bar on the first substrate.

8. The electrical system of claim 7 , wherein:

the first bus bar comprises a positive reference voltage rail of a direct current (DC) voltage bus; and

the second bus bar comprises a negative reference voltage rail of the DC voltage bus;

the first terminal comprises a drain terminal of the first field effect transistor; and

the second terminal comprises a source terminal of the second field effect transistor.

9. The electrical system of claim 6 , wherein the first field effect transistor and the second field effect transistor comprise surface mount devices mounted on a side of the second substrate facing the second side.

10. The electrical system of claim 9 , wherein the one or more capacitors comprise one or more electrolytic capacitors.

11. An electrical system comprising:

a first substrate comprising:

a pair of voltage rails configured to provide a voltage bus;

one or more capacitive elements coupled between the pair of voltage rails to provide a direct current (DC) link capacitance; and

a first plurality of connection interfaces electrically connected to a first voltage rail of the pair;

a second plurality of connection interfaces electrically connected to a second voltage rail of the pair, wherein the second plurality of connection interfaces are interleaved with the first plurality of connection interfaces; and

a second substrate comprising

a third plurality of connection interfaces electrically connected to the first plurality of connection interfaces;

a fourth plurality of connection interfaces electrically connected to the second plurality of connection interfaces, wherein the fourth plurality of connection interfaces are interleaved with the third plurality of connection interfaces; and

a power conversion arrangement coupled to the third plurality of connection interfaces and the fourth plurality of connection interfaces.

12. The electrical system of claim 11 , wherein the one or more capacitive elements are provided on a first side of the first substrate and the first plurality of connection interfaces and the second plurality of connection interfaces are provided on a second side of the first substrate opposite the first side.

13. The electrical system of claim 12 , wherein the third plurality of connection interfaces, the fourth plurality of connection interfaces, and the power conversion arrangement are provided on a third side of the second substrate facing the second side of the first substrate.

14. The electrical system of claim 13 , wherein:

the one or more capacitive elements comprise one or more electrolytic capacitors; and

the power conversion arrangement comprises a plurality of surface mount devices.

15. The electrical system of claim 11 , further comprising:

an electric motor coupled to the power conversion arrangement; and

a flow control device having a rotary shaft coupled to a rotor of the electric motor, wherein the power conversion arrangement comprises a plurality of switching elements operable to actuate the rotor of the electric motor.

16. The electrical system of claim 15 , wherein:

the voltage bus comprises a 48 Volt bus; and

the flow control device comprises at least one of a compressor and a turbine.

17. The electrical system of claim 16 , further comprising a control module coupled to the power conversion arrangement to operate the plurality of switching elements using pulse width modulation.

18. An electrical system comprising:

a first substrate comprising one or more capacitors on a first side of the first substrate and a first plurality of connection interfaces on a second side of the first substrate opposite the first side, wherein:

a first electrode of the one or more capacitors is coupled to a first bus bar on the first side of the first substrate;

a second electrode of the one or more capacitors is coupled to a second bus bar on the second side of the first substrate;

a first subset of the first plurality of connection interfaces is electrically connected to the first bus bar;

a second subset of the first plurality of connection interfaces is electrically connected to the second bus bar; and

connection interfaces of the first subset are alternately interposed with connection interfaces of the second subset; and

a second substrate comprising a second plurality of connection interfaces, wherein:

a third subset of the second plurality of connection interfaces is coupled to the first subset of the second plurality of connection interfaces;

a fourth subset of the second plurality of connection interfaces is coupled to the second subset of the second plurality of connection interfaces;

a first switching element is coupled between the third subset of the second plurality of connection interfaces and an output node;

a second switching element is coupled between the output node and the fourth subset; and

connection interfaces of the third subset are alternately interposed with connection interfaces of the fourth subset.

19. The electrical system of claim 18 , wherein the one or more capacitors comprise a direct current (DC) link capacitor.

20. The electrical system of claim 18 , wherein the first switching element and the second switching element are surface mounted to a third side of the second substrate facing the second side of the first substrate.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE TYPOS IN THE APPLICATION NUMBER PREVIOUSLY RECORDED AT REEL: 056111 FRAME: 0583. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 25, 2022
From: GARRETT TRANSPORTATION I INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 059250/0792 →
SECURITY AGREEMENT Recorded May 3, 2021
From: GARRETT TRANSPORTATION I INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 056111/0583 →
RELEASE OF SECURITY INTEREST Recorded Apr 30, 2021
From: WILMINGTON SAVINGS FUND SOCIETY, FSB
To: GARRETT TRANSPORTATION I INC.
Reel/Frame 056427/0298 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 15, 2021
From: JPMORGAN CHASE BANK, N.A., AS RESIGNING ADMINISTRATIVE AND COLLATERAL AGENT
To: WILMINGTON SAVINGS FUND SOCIETY, FSB, AS SUCCESSOR ADMINISTRATIVE AND COLLATERAL AGENT
Reel/Frame 055008/0263 →
SECURITY INTEREST Recorded Oct 1, 2018
From: GARRETT TRANSPORTATION I INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 047172/0220 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 6, 2018
From: HONEYWELL INTERNATIONAL INC.
To: GARRETT TRANSPORTATION I INC.
Reel/Frame 047024/0127 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE FROM CHANGE OF NAME TO ASSIGNMENT AND "1" TO "I" IN ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 046103 FRAME: 0590. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 30, 2018
From: HONEYWELL INTERNATIONAL INC.
To: GARRETT TRANSPORTATION I INC.
Reel/Frame 046867/0656 →
CHANGE OF NAME Recorded Jun 15, 2018
From: HONEYWELL INTERNATIONAL INC.
To: GARRETT TRANSPORTATION 1 INC.
Reel/Frame 046103/0590 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 13, 2017
From: MOHAMMADPOUR, ALI; LOVE, ANDREW; PU, LOUIS; GUIDRY, MIKE
To: HONEYWELL INTERNATIONAL INC.
Reel/Frame 043863/0269 →
Cited By (1)
US 12,207,409