Dynamic memory reallocation for match-action packet processing
View Patent ↗A pool of unit memories is provided in order to flexibly allocate memory capacity to implement various tables and/or logical memories such as those for implementing an OpenFlow switch. The pool is structured with routing resources for allowing flexible allocation and reallocation of memory capacity to the various tables. The unit memories and logical units in the pool are interconnected by a set of horizontal routing resources and a set of vertical routing resources.
1. A hardware forwarding element comprising a plurality of match-action stages, each match-action stage comprising a set of match-action tables, the hardware forwarding element comprising:
a plurality of unit memories that are organized into a plurality of rows;
a plurality of logical units (LUs) to implement at least a subset of the match action tables, each LU allocated a set of the unit memories, each LU aligned with a row of the unit memories; and
a routing structure for providing each LU with access to a set of unit memories allocated to the LU, the routing structure comprising:
a first vertical bus for providing each LU with a row above the LU's associated row access to at least one allocated unit memory in the above row; and
a second vertical bus for providing each LU with a row below the LU's associated row access to at least one allocated unit memory in the row below, the second vertical bus being a separate, different bus from the first vertical bus,
each of the first and second vertical buses comprising a read path and a write path.
2. The hardware forwarding element of claim 1 , wherein the routing structure further comprises, for each row of unit memories:
a first horizontal bus for connecting unit memories of the row to the LU aligned with the row; and
second and third horizontal buses for connecting unit memories of the row to LUs not aligned with the row.
3. The hardware forwarding element of claim 2 , wherein the second horizontal bus is for connecting unit memories of the row to a first LU below the row through the first vertical bus.
4. The hardware forwarding element of claim 2 , wherein the second horizontal bus is for connecting unit memories of the row to a first LU above the row through the second vertical bus.
5. The hardware forwarding element of claim 2 , wherein the third horizontal bus is for connecting unit memories of the row to a first LU below the row through a third vertical bus of the routing structure when a data flow at the first LU's associated row exceeds a particular threshold, the third vertical bus being a separate, different bus from the first and second vertical buses.
6. The hardware forwarding element of claim 2 , wherein a particular row of unit memories of the plurality of rows has N additional LUs aligned with the row and N additional horizontal buses, each additional horizontal bus for connecting unit memories of the particular row to a different additional LU.
7. The hardware forwarding element of claim 2 , wherein each of the first, second, and third horizontal buses comprises a read path and a write path.
8. The hardware forwarding element of claim 2 , wherein the second and third horizontal buses are each connected to at least one vertical bus at a multiplexer for controlling data access.
9. The hardware forwarding element of claim 8 , wherein the first and second vertical buses comprise multiplexers at each row for selecting between data from different rows.
10. The hardware forwarding element of claim 9 , wherein the first and second vertical buses are partitioned by the multiplexers at each row into a plurality sections that can be used by different LUs simultaneously.
11. The hardware forwarding element of claim 9 , wherein the multiplexers are configured such that only one unit memory is able drive its read data to a particular LU at a time.
12. The hardware forwarding element of claim 1 , wherein each of a plurality of LUs is configured to implement flow tables to store flow entries for forwarding packets, the configured LUs implementing the flow tables by using the routing resources to read and write from unit memories assigned to the LU.
13. The hardware forwarding element of claim 1 , wherein the routing structure and the plurality of LUs are configured by a controller.
14. The hardware forwarding element of claim 13 , wherein each bus is associated with a set of multiplexers for providing read and write access and configuring the routing structure comprises configuring a plurality of multiplexers of the routing structure.
15. The hardware forwarding element of claim 13 , wherein the controller is a local configuration register on the hardware forwarding element.
16. The hardware forwarding element of claim 1 , wherein the hardware forwarding element is a hardware switching element.
17. The hardware forwarding element of claim 1 , wherein the routing structure further comprises a third vertical bus for providing each LU access to its allocated unit memories located above the LU's associated row when a data flow at the LU's associated row exceeds a certain threshold, the third vertical bus being a separate, different bus from the first and second vertical buses.
18. The hardware forwarding element of claim 17 , wherein the third vertical bus comprises a read path and a write path.
19. The hardware forwarding element of claim 1 , wherein at least a subset of the LUs are arithmetic logical units (ALUs).
20. The hardware forwarding element of claim 1 , wherein the unit memories are random access memory (RAM).