IP Library Granted Patent US 10,394,710
Granted Patent B2
US 10,394,710 · App. 15/786,356 · Granted Aug 27, 2019

Storage class memory (SCM) memory mode cache system

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Quick Facts
Patent No.
US 10,394,710
App. No.
15/786,356
Granted
Aug 27, 2019
Kind
B2
Abstract

An SCM memory mode NVDIMM-N cache system includes an SCM subsystem, and an NVDIMM-N subsystem having at volatile memory device(s) and non-volatile memory device(s). A memory controller writes data to the volatile memory device(s) and, in response, updates a cache tracking database. The memory controller then writes a subset of the data to the SCM subsystem subsequent to the writing of that data to the volatile memory device(s) and, in response, updates the cache tracking database. The memory controller then receives a shutdown signal and, in response, copies the cache tracking database to the volatile memory device(s) in the NVDIMM-N subsystem. The NVDIMM-N subsystem then copies at least some of the data and the cache tracking database from the volatile memory device(s) to the non-volatile memory device(s) prior to shutdown. The data and the cache tracking database may then be retrieved from non-volatile memory device(s) when the system is restored.

Claims (45)

1. A Storage Class Memory (SCM) memory mode persistent memory cache system, comprising:

a first Storage Class Memory (SCM) subsystem that provides first data communication speeds;

a persistent memory subsystem that includes at least one non-volatile memory device and that provides second data communication speeds that are greater than the first data communication speeds; and

a memory controller that is coupled to the first SCM subsystem and the persistent memory subsystem, wherein the memory controller is configured to:

write a plurality of data to the persistent memory subsystem and, in response, update a cache tracking database;

write a first subset of the plurality of data to the first SCM subsystem subsequent to the writing of the plurality of data to the persistent memory subsystem and, in response, update the cache tracking database; and

receive a shutdown signal and, in response, copy the cache tracking database to the persistent memory subsystem, wherein the persistent memory subsystem is configured to store at least some of the plurality of data and the cache tracking database in the at least one non-volatile memory device during a shutdown associated with the shutdown signal.

2. The system of claim 1 , wherein the at least one non-volatile memory device in the persistent memory subsystem is part of at least one of a Non-Volatile Dual Inline Memory Module (NVDIMM-N) subsystem, a Random Access Memory (RAM) subsystem, a memristor subsystem, and a second SCM subsystem.

3. The system of claim 1 , wherein the memory controller is configured to:

erase the first subset of the plurality of data from the persistent memory subsystem in response to writing the first subset of the plurality of data to the first SCM subsystem, wherein the erasing of the first subset of the plurality of data from the persistent memory subsystem provides a second subset of the plurality of data on the persistent memory subsystem.

4. The system of claim 3 , wherein the cache tracking database details storage locations and statuses of the first subset of the plurality of data on the first SCM subsystem and the second subset of the plurality of data on the persistent memory subsystem.

5. The system of claim 1 , wherein the first data communications speeds and the second data communication speeds each include at least one of: data read speeds associated with data reads by the memory controller, and data write speeds associated with data writes by the memory controller.

6. The system of claim 1 , wherein the memory controller is configured, in response to an initialization that is subsequent to the shutdown, to retrieve the cache tracking database from the persistent memory subsystem and copy the at least some of the plurality of data from the persistent memory subsystem to the SCM subsystem.

7. The system of claim 6 , further comprising:

a Basic Input/Output System (BIOS) that is configured to determine that the memory controller has copied the at least some of the plurality of data from the persistent memory subsystem to the SCM subsystem and, in response, erase the at least some of the plurality of data from the persistent memory subsystem.

8. An Information Handling System (IHS), comprising:

a chassis;

a memory system that is located in the chassis and that includes:

a first Storage Class Memory (SCM) subsystem that provides first data communication speeds;

a persistent memory subsystem that includes at least one non-volatile memory device and that provides second data communication speeds that are greater than the first data communication speeds; and

a processing system that is coupled to the memory system and that is configured to:

write a plurality of data to the persistent memory subsystem and, in response, update a cache tracking database;

write a first subset of the plurality of data to the first SCM subsystem subsequent to the writing of the plurality of data to the persistent memory subsystem and, in response, update the cache tracking database; and

receive a shutdown signal and, in response, copy the cache tracking database to the persistent memory subsystem, wherein the persistent memory subsystem is configured to store at least some of the plurality of data and the cache tracking database in the at least one non-volatile memory device during a shutdown associated with the shutdown signal.

9. The IHS of claim 8 , wherein the at least one non-volatile memory device in the persistent memory subsystem is part of at least one of: a Non-Volatile Dual Inline Memory Module (NVDIMM-N) subsystem, a Random Access Memory (RAM) subsystem, a memristor subsystem, and a second SCM subsystem.

10. The IHS of claim 8 , wherein the processing system is configured to:

erase the first subset of the plurality of data from the persistent memory subsystem in response to writing the first subset of the plurality of data to the first SCM subsystem, wherein the erasing of the first subset of the plurality of data from the persistent memory subsystem provides a second subset of the plurality of data on the persistent memory subsystem.

11. The IHS of claim 10 , wherein the cache tracking database details storage locations and statuses of the first subset of the plurality of data on the first SCM subsystem and the second subset of the plurality of data on the persistent memory subsystem.

12. The IHS of claim 8 , wherein the processing system is configured, in response to an initialization that is subsequent to the shutdown, to retrieve the cache tracking database from the persistent memory subsystem and copy the at least some of the plurality of data from the persistent memory subsystem to the SCM subsystem.

13. The IHS of claim 12 , further comprising:

a Basic Input/Output System (BIOS) that is configured to determine that the processing system has copied the at least some of the plurality of data from the persistent memory subsystem to the SCM subsystem and, in response, erase the at least some of the plurality of data from the persistent memory subsystem.

14. A method for providing a Storage Class Memory (SCM) memory mode persistent memory cache, comprising:

writing, by a memory controller to a persistent memory subsystem that provides second data communication speeds, a plurality of data and, in response, updating a cache tracking database;

writing, by the memory controller subsequent to the writing of the plurality of data to the persistent memory subsystem and to an Storage Class Memory (SCM) subsystem that provides first data communication speeds that are less than the second data communication speeds, a first subset of the plurality of data to the first SCM subsystem and, in response, updating the cache tracking database;

receiving, by the memory controller, a shutdown signal and, in response, copying the cache tracking database to the persistent memory subsystem; and

storing, by the persistent memory subsystem, at least some of the plurality of data and the cache tracking database in at least one non-volatile memory device during a shutdown associated with the shutdown signal.

15. The method of claim 14 , wherein the at least one non-volatile memory device in the persistent memory subsystem is part of at least one of: a Non-Volatile Dual Inline Memory Module (NVDIMM-N) subsystem, a Random Access Memory (RAM) subsystem, a memristor subsystem, and a second SCM subsystem.

16. The method of claim 14 , further comprising:

erasing, by the memory controller, the first subset of the plurality of data from the persistent memory subsystem in response to writing the first subset of the plurality of data to the first SCM subsystem, wherein the erasing of the first subset of the plurality of data from the persistent memory subsystem provides a second subset of the plurality of data on the persistent memory subsystem.

17. The method of claim 16 , wherein the cache tracking database details storage locations and statuses of the first subset of the plurality of data on the first SCM subsystem and the second subset of the plurality of data on the persistent memory subsystem.

18. The method of claim 14 , wherein the first data communications speeds and the second data communication speeds each include at least one of: data read speeds associated with data reads by the memory controller, and data write speeds associated with data writes by the memory controller.

19. The method of claim 14 , further comprising:

retrieving, by the memory controller in response to an initialization that is subsequent to the shutdown, the cache tracking database from the persistent memory subsystem and copying the at least some of the plurality of data from the persistent memory subsystem to the SCM subsystem.

20. The method of claim 19 , further comprising

determining, by a Basic Input/Output System (BIOS), that the memory controller has copied the at least some of the plurality of data from the persistent memory subsystem to the SCM subsystem and, in response, erasing the at least some of the plurality of data from the persistent memory subsystem.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (044535/0109) Recorded May 20, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO WYSE TECHNOLOGY L.L.C.)
Reel/Frame 060753/0414 →
RELEASE OF SECURITY INTEREST AT REEL 044535 FRAME 0001 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; WYSE TECHNOLOGY L.L.C.
Reel/Frame 058298/0475 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Nov 29, 2017
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 044535/0109 →
PATENT SECURITY AGREEMENT (CREDIT) Recorded Nov 29, 2017
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; WYSE TECHNOLOGY L.L.C.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 044535/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 17, 2017
From: BERKE, STUART ALLEN; JENNE, JOHN E.
To: DELL PRODUCTS L.P.
Reel/Frame 043886/0832 →