Multi-layer single chip MEMS WLCSP fabrication
A method for fabricating a WLCSP device includes receiving a MEMS cap wafer having a first radius, a MEMS device wafer having a second radius, and a CMOS substrate wafer having a third radius, wherein the first radius is smaller than the second radius, and wherein the second radius is smaller than the third radius, disposing the MEMS cap wafer approximately concentrically upon the MEMS device wafer, disposing the MEMS device wafer approximately concentrically upon the CMOS substrate wafer, disposing a spacer structure upon the MEMS device wafer, wherein the spacer structure comprises a plurality of proximity spacers disposed upon a proximity flag, wherein the plurality of proximity spacers are disposed upon the MEMS device wafer, disposing a mask layer in contact to the plurality of proximity spacers, above and substantially parallel to the MEMS cap wafer, and forming a pattern upon the MEMS cap wafer using the mask layer.
1. A method for fabricating a multi-layer wafer level chip scale package for MEMS devices comprising:
receiving a MEMS cap wafer comprising a plurality of MEMS capping structures, a MEMS device wafer comprising a plurality of MEMS dies, and a CMOS substrate wafer comprising a plurality of CMOS dies, wherein the CMOS substrate wafer is characterized by a first radius, wherein the MEMS device layer is characterized by a second radius, and wherein the MEMS cap wafer is characterized by a third radius, wherein the first radius is greater than the second radius, and wherein the second radius is greater than the third radius;
forming a multi-layer wafer comprising the MEMS cap wafer disposed approximately concentrically upon the MEMS device wafer, and the MEMS device wafer disposed approximately concentrically upon the CMOS substrate wafer, wherein a MEMS device comprises a MEMS capping structure, a MEMS die and a CMOS die;
disposing a spacer structure upon the multi-layer wafer, wherein the spacer structure comprises a plurality of proximity spacers disposed upon a proximity flag, wherein the plurality of proximity spacers are disposed upon the MEMS device layer;
disposing a mask layer above and substantially parallel to the MEMS cap wafer, wherein the mask layer is disposed upon the plurality of proximity spacers; and
forming a pattern upon the MEMS cap wafer using the mask layer.
2. The method of claim 1 wherein a width of the proximity spacer is smaller than an approximate difference between the second radius and the third radius.
3. The method of claim 1 wherein the pattern comprises a metallization pattern.
4. The method of claim 3 further comprising forming a metallization layer upon the MEMS cap wafer in response to the metallization pattern.
5. The method of claim 1 :
wherein the forming the pattern comprises forming a metallization pattern upon the MEMS cap wafer using the mask layer; and
wherein the method further comprises disposing the multi-layer wafer within a back side processing tool, wherein the back side processing tool comprises a plurality of side-walls, and a cavity wall, wherein the multi-layer wafer is suspended by a front side of the CMOS substrate wafer by the plurality of side-walls, wherein the metallization pattern is disposed a distance away from the cavity wall, wherein the distance is within a range of about 0 to about 50 microns.
6. The method of claim 5 wherein the metallization layer is disposed a non-zero distance away from the cavity wall.
7. The method of claim 5 further comprising processing a back side of the CMOS wafer while the multi-layered wafer is disposed within the back side processing tool.
8. The method of claim 1 further comprising:
forming a plurality of MEMS capping structures upon a first surface of an MEMS cap wafer; and
forming a plurality of grooves in the first surface of the MEMS cap wafer, wherein the plurality of grooves are associated with the MEMS capping structure.
9. The method of claim 8
wherein the forming the pattern upon the MEMS cap wafer comprises forming the pattern upon a second surface of the MEMS cap wafer;
wherein the method further comprises singulating the MEMS device by applying a wafer saw to the second surface of the MEMS cap wafer at locations corresponding to the plurality of grooves formed in the first surface of the MEMS cap wafer, wherein chipping of the MEMS cap wafer is reduced by the plurality of grooves.
10. The method of claim 8
wherein forming the plurality of grooves in the first surface of the MEMS cap wafer comprises forming a plurality of multi-tiered grooves in the first surface of the MEMS cap.
11. A method for wafer level chip scale packages for MEMS devices comprising:
receiving a CMOS substrate wafer comprising a plurality of CMOS dies, wherein the CMOS substrate wafer is characterized by a first radius;
receiving a MEMS device wafer comprising a plurality of MEMS dies, wherein the MEMS device wafer is characterized by a second radius, and wherein the first radius exceeds the second radius;
disposing the MEMS device wafer approximately concentrically upon the CMOS substrate wafer;
receiving a MEMS cap wafer comprising a plurality of MEMS capping structures, wherein the MEMS cap wafer is characterized by a third radius, and wherein the second radius exceeds the third radius;
disposing the MEMS cap wafer approximately concentrically upon the MEMS device wafer, wherein a portion of the MEMS device wafer remains exposed;
disposing a spacer structure in contact with the portion of the MEMS device wafer;
disposing a first mask pattern above the MEMS cap wafer but not in contact therewith, wherein the first mask pattern contacts the spacer structure; and
forming a metallization layer upon the MEMS cap wafer using the first mask pattern;
wherein a MEMS device comprises a CMOS die, a MEMS die, and a MEMS capping structure.
12. The method of claim 11
wherein the spacer structure comprises a plurality of proximity spacers associated with a width; and
wherein the width is smaller than approximate difference between the second radius and the third radius.
13. The method of claim 11 wherein the metallization layer comprises a plurality of solder structures.
14. The method of claim 3 further wherein the plurality of solder structures comprises a plurality of solder balls.
15. The method of claim 13 wherein the method further comprises disposing the multi-layer wafer within a back side processing tool, wherein the back side processing tool comprises a plurality of side-walls, and a bottom cavity wall, wherein the multi-layer wafer is suspended by a front side of the CMOS substrate wafer by the plurality of side-walls, wherein the plurality of solder balls are disposed a distance away from the bottom cavity wall, wherein the distance is within a range of about 0 to about 50 microns, and wherein a back side of the CMOS substrate wafer is exposed.
16. The method of claim 15 further comprising processing the back side of the CMOS wafer while the multi-layered wafer is disposed within the back side processing tool.
17. The method of claim 11 further comprising:
forming a plurality of MEMS capping structures upon a first surface of a MEMS cap wafer; and
forming a plurality of grooves within the first surface of the MEMS cap wafer, wherein the plurality of grooves are associated with a MEMS capping structure.
18. The method of claim 17 wherein disposing the MEMS cap wafer approximately concentrically upon the MEMS device wafer comprises disposing the first surface of the MEMS cap wafer upon the MEMS device wafer.
19. The method of claim 17 further comprising applying a wafer saw to singulate the MEMS device at locations corresponding to grooves formed in the first surface of the MEMS cap wafer, wherein chipping of the MEMS cap wafer is reduced by the grooves.
20. The method of claim 17 wherein forming the plurality of grooves in the first surface of the MEMS cap wafer comprises forming a plurality of multi-tiered grooves in the first surface of the MEMS cap.