Integration of NVMe device with DRAM cache system and method
A method, computer program product, and computer system for executing one of a reboot and a startup process. A write I/O may be received at a DRAM cache. Data may be written to at least two different NVMe devices. When the data of the write I/O is completely written to the at least two different NVMe devices, a response may be sent to a driver layer.
1. A computer-implemented method comprising:
executing, by a computing device, one of a reboot and a startup process;
receiving a write I/O at a DRAM cache;
writing data of the write I/O to at least two different Non-Volatile Memory Express (NVMe) devices, wherein a first NVMe device of the at least two different NVMe devices is housed in a first storage processor and a second NVMe device of the at least two different NVMe devices is housed in a second storage processor, wherein the first NVMe device of the at least two different NVMe devices is concurrently coupled to a first CPU housed within the first storage processor and a second CPU housed within the second storage processor directly through dual PCI-E ports located within the first NVMe device of the at least two different NVMe devices and the second NVMe device of the at least two different NVMe devices is concurrently coupled to the second CPU housed within the second storage processor and the first CPU housed within the first storage processor directly through dual PCI-E ports located within the second NVMe device of the at least two different NVMe devices; and
sending, when the data of the write I/O is completely written to the at least two different NVMe devices, a response to a driver layer.
2. The computer-implemented method of claim 1 wherein one of the reboot and the startup process is executed only via the first storage processor.
3. The computer-implemented method of claim 2 wherein executing includes verifying that one or more parameters of the second storage processor match the first storage processor, wherein the one or more parameters comprise a clean cache page number, a dirty cache page number, and a metadata memory size.
4. The computer-implemented method of claim 3 wherein executing further includes transferring cache page metadata from the second storage processor to the first storage processor.
5. The computer-implemented method of claim 1 wherein one of the reboot and the startup process is executed via a dual storage processor including a first storage processor and a second storage processor.
6. The computer-implemented method of claim 5 wherein executing includes syncing memory allocation with the first storage processor and the second storage processor.
7. The computer-implemented method of claim 1 further comprising:
determining whether the write I/O received at the DRAM cache is one of a write miss, a clean page write hit, and a dirty page write hit by searching a hash table.
8. A computer program product residing on a non-transitory computer readable storage medium having a plurality of instructions stored thereon which, when executed across one or more processors, causes at least a portion of the one or more processors to perform operations comprising:
executing, by a computing device, one of a reboot and a startup process;
receiving a write I/O at a DRAM cache;
writing data of the write I/O to at least two different Non-Volatile Memory Express (NVMe) devices, wherein a first NVMe device of the at least two different NVMe devices is housed in a first storage processor and a second NVMe device of the at least two different NVMe devices is housed in a second storage processor, wherein the first NVMe device of the at least two different NVMe devices is concurrently coupled to a first CPU housed within the first storage processor and a second CPU housed within the second storage processor directly through dual PCI-E ports located within the first NVMe device of the at least two different NVMe devices and the second NVMe device of the at least two different NVMe devices is concurrently coupled to the second CPU housed within the second storage processor and the first CPU housed within the first storage processor directly through dual PCI-E ports located within the second NVMe device of the at least two different NVMe devices; and
sending, when the data of the write I/O is completely written to the at least two different NVMe devices, a response to a driver layer.
9. The computer program product of claim 8 wherein one of the reboot and the startup process is executed only via the first storage processor.
10. The computer program product of claim 9 wherein executing includes verifying that one or more parameters of the second storage processor match the first storage processor.
11. The computer program product of claim 10 wherein executing further includes transferring cache page metadata from the second storage processor to the first storage processor.
12. The computer program product of claim 8 wherein one of the reboot and the startup process is executed via a dual storage processor including a first storage processor and a second storage processor.
13. The computer program product of claim 12 wherein executing includes syncing memory allocation with the first storage processor and the second storage processor.
14. The computer program product of claim 8 wherein the operations further include:
determining whether the write I/O received at the DRAM cache is one of a write miss, a clean page write hit, and a dirty page write hit by searching a hash table.
15. A computing system including one or more processors and one or more memories configured to perform operations comprising:
executing, by a computing device, one of a reboot and a startup process;
receiving a write I/O at a DRAM cache;
writing data of the write I/O to at least two different Non-Volatile Memory Express (NVMe) devices, wherein a first NVMe device of the at least two different NVMe devices is housed in a first storage processor and a second NVMe device of the at least two different NVMe devices is housed in a second storage processor, wherein the first NVMe device of the at least two different NVMe devices is concurrently coupled to a first CPU housed within the first storage processor and a second CPU housed within the second storage processor directly through dual PCI-E ports located within the first NVMe device of the at least two different NVMe devices and the second NVMe device of the at least two different NVMe devices is concurrently coupled to the second CPU housed within the second storage processor and the first CPU housed within the first storage processor directly through dual PCI-E ports located within the second NVMe device of the at least two different NVMe devices; and
sending, when the data of the write I/O is completely written to the at least two different NVMe devices, a response to a driver layer.
16. The computing system of claim 15 wherein one of the reboot and the startup process is executed only via the first storage processor.
17. The computing system of claim 16 wherein executing includes verifying that one or more parameters of the second storage processor match the first storage processor and transferring cache page metadata from the second storage processor to the first storage processor.
18. The computing system of claim 15 wherein one of the reboot and the startup process is executed via a dual storage processor including a first storage processor and a second storage processor.
19. The computing system of claim 15 wherein the operations further include:
determining whether the write I/O received at the DRAM cache is one of a write miss, a clean page write hit, and a dirty page write hit by searching a hash table.
20. The computer-implemented method of claim 1 wherein the first NVMe device of the at least two different NVMe devices and the second NVMe device of the at least two different NVMe devices each comprise a data namespace portion and a metadata namespace portion, wherein the metadata namespace portion is configured to store DRAM Cache metadata for the DRAM when either the first storage processor or the second storage processor is shutdown or in a panic state.