IP Library Granted Patent US 10,235,000
Granted Patent B2
US 10,235,000 · App. 15/789,103 · Granted Mar 19, 2019

Sensing system and semiconductor device

Inventors: Nobukazu Tanaka (Tokyo, JP); Takayuki Noto (Tokyo, JP); Tetsuo Tanemura (Tokyo, JP)
Assignee: SYNAPTICS INCORPORATED
G06F3/044G06F3/0416
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Quick Facts
Patent No.
US 10,235,000
App. No.
15/789,103
Granted
Mar 19, 2019
Kind
B2
Abstract

A sensing system includes: a transmitter circuitry configured to transmit drive signals to N sensors, N being a positive integer; N receiver circuitries configured to receive in parallel N sense signals generated in response to the drive signals by N sensors, N being a positive integer; N modulation circuitries configured to modulate outputs of the N receiver circuitries; a mixer circuitry configured to mix outputs of the N modulation circuitries; an A/D converter circuitry configured to receive an output of the mixer circuitry; and a demodulation circuitry. The demodulation circuitry is configured to demodulate an output of the A/D converter circuitry to generate N digital sense values corresponding to the N sense signals.

Claims (79)

1. A sensing system, comprising:

transmitter circuitry configured to transmit drive signals to N sensors, N being a positive integer;

N receiver circuitries configured to receive in parallel N sense signals generated in response to the drive signals by the N sensors;

N modulation circuitries configured to modulate outputs of the N receiver circuitries;

mixer circuitry configured to mix outputs of the N modulation circuitries;

A/D converter circuitry configured to receive an output of the mixer circuitry; and

demodulation circuitry configured to demodulate an output of the A/D converter circuitry to generate N digital sense values corresponding to the N sense signals.

2. The sensing system according to claim 1 ,

wherein the transmitter circuitry is configured to repeatedly transmit the drive signals to the N sensors, respectively, at least over N cycles, and

wherein the N receiver circuitries are configured to respectively receive the N sense signals over the N cycles.

3. The sensing system according to claim 2 ,

wherein the N modulation circuitries are configured to perform code-modulation on the outputs of the N receiver circuitries, respectively.

4. The sensing system according to claim 2 , wherein each of the N cycles is based on modulation coefficients represented by an N-row and N-column matrix; and

wherein the N modulation circuitries are further configured to sequentially supply to the mixer circuitry N products obtained by multiplying the N sense signals and respective elements of the matrix in the first to N th rows, respectively.

5. The sensing system according to claim 4 ,

wherein the mixer circuitry is further configured to calculate a sum of N products in each of the N cycles and supply the calculated sum to the A/D converter circuitry over the N cycles.

6. The sensing system according to claim 5 ,

wherein the A/D converter circuitry is further configured to sequentially output a digital value corresponding to the output of the mixer circuitry in each of the N cycle, to thereby output N digital signals over the N cycles,

wherein the demodulation circuitry is further configured to receive demodulation coefficients represented by an N-row and N-column matrix which is orthogonal to the matrix of the modulation coefficients, and

wherein the demodulation circuitry is further configured to use the N digital signals supplied over the N cycle as an N-row and one-column input matrix and output the N digital sense values by multiplying the demodulation coefficients and the N-row and one-column input matrix.

7. The sensing system according to claim 6 ,

wherein the demodulation circuitry comprises:

N−1 serially-connected delay circuitries configured to delay the N digital signals supplied over the N cycles by one cycle; and

N product-sum calculation circuitries configured to output the N digital sense values by multiplying outputs of the A/D converter circuitry and N−1 serially-connected delay circuitries by the N elements of each of the first to N th rows of the demodulation coefficients to generate products and accumulating the products.

8. The sensing system according to claim 6 ,

wherein the A/D converter circuitry is further configured to perform delta-sigma conversion operations K times in each of the N cycles and output K digital data as the digital signals in each cycle over the N cycles,

wherein the demodulation circuitry further comprises N multiplier circuitries and N filter circuitries configured to receive the outputs of the N multiplier circuits, respectively, and

wherein each of the filter circuitries further comprises a first-order integration circuit and a K×N-order comb filter which are cascade-connected.

9. The sensing system according to claim 6 ,

wherein the A/D converter circuitry is further configured to perform delta-sigma conversion operations K times in each of the N cycles, and output K digital data as the digital signals in each cycle over the N cycles,

wherein the demodulation circuitry further comprises N multiplier circuitries and N filter circuitries configured to receive the outputs of the N multiplier circuitries, respectively, and

wherein each of the filter circuitries further comprises a first-order integration circuit, a 1/D decimator circuit and a K×N/D-order comb filter, which are cascade-connected.

10. The sensing system according to claim 6 ,

wherein the A/D converter circuitry is further configured to perform delta-sigma conversion operations K times in each of the N cycles, and output K one-bit digital data as the digital signals in each cycle over the N cycles,

wherein the demodulation circuitry further comprises N multiplier circuitries and N filter circuitries configured to receive the outputs of the N multiplier circuitries, respectively, and

wherein each of the filter circuitries further comprises a first-order integration circuit, a 1/D decimator circuit and a K×N/D-order comb filter which are cascade-connected.

11. The sensing system according to claim 6 ,

wherein the A/D converter circuitry is further configured to perform delta-sigma conversion operations K times in each of the N cycles, and output K one-bit digital data as the digital signals in each cycle over the N cycles,

wherein the demodulation circuitry further comprises a counter which adds or subtracts the K one-bit digital data over the N cycles based on the values of the N elements of each of the N rows of the demodulation coefficients.

12. The sensing system according to claim 11 ,

wherein D is equal to N×K.

13. The sensing system according to claim 2 ,

wherein a waveform of each of the drive signals in each of the N cycle is unchanged over the N cycles.

14. A semiconductor device, comprising:

a transmitter circuitry configured to transmit drive signals to N sensor capacitors of a touch panel, N being a positive integer;

N receiver circuitries configured to receive in parallel N sense signals generated in response to the drive signals by the N sensor capacitors;

N modulation circuitries configured to modulate outputs of the N receiver circuitries;

a mixer circuitry configured to mix outputs of the N modulation circuitries;

an A/D converter circuitry configured to receive an output of the mixer circuitry; and

a demodulation circuitry configured to demodulate an output of the A/D converter circuitry to generate N digital sense values corresponding to the N sense signals.

15. The semiconductor device according to claim 14 ,

wherein the transmitter circuitry is further configured to repeatedly transmit the drive signals to the N sensors, respectively, at least over N cycles, and

wherein the N receiver circuitries are further configured to respectively receive the N sense signals over the N cycles.

16. The semiconductor device according to claim 15 , wherein each of the N cycles is based on modulation coefficients represented by an N-row and N-column matrix; and

wherein N modulation circuitries are further configured sequentially supply to the mixer circuitry N products obtained by multiplying the N sense signals by respective elements of the first to N th rows of the modulation coefficients, respectively.

17. The semiconductor device according to claim 14 , further comprising:

a multiplexer; and

M sets of terminals, each set including N terminals for M being a positive integer,

wherein the touch panel comprises M×N sensor capacitors associated with the M×N terminals,

wherein the multiplexer is configured to sequentially select N terminals from the respective M sets of the terminals and sequentially connect the associated N sensor capacitors to the touch sensing circuitry.

18. The semiconductor device according to claim 14 , further comprising:

M touch sensing circuitries each including the transmitter circuitry, the N receiver circuitries, the N modulation circuitries, the mixer circuitry, the A/D converter circuitry, and the demodulation circuitry; and

M×N terminals,

wherein the touch panel comprises M×N capacitors respectively connected to the M×N terminals, and wherein M×N terminals provide connections between the M touch sensing circuitries and the M×N capacitors.

19. The semiconductor device according to claim 14 , further comprising:

X transmitting terminals, X being a positive integer; and

L×N receiving terminals;

wherein the touch panel comprises a mutual capacitance touch panel comprising X rows of sensor capacitors, each row including L×N sensor capacitors,

wherein the L×N sensor capacitors of each of the X rows are connected to the L×N receiving terminals, respectively,

wherein the transmitter circuitry is configured to sequentially transmit the drive signals to the respective X rows of the sensor capacitors from the X transmitting terminals, and

wherein the touch sensing circuitry further comprises L circuit sets each comprising the N receiver circuitries, the modulation circuitry, the mixer circuitry, the A/D converter circuitry and the demodulation circuitry, to accommodate N of the L×N receiving terminals.

20. The semiconductor device according to claim 15 , further comprising:

X transmitting terminals, X being a positive integer;

L sets of receiving terminals, each set comprising N receiving terminals, L being a positive integer; and

a multiplexer,

wherein the touch panel comprises a mutual capacitance touch panel comprising X rows of sensor capacitors, each row including L×N sensor capacitors,

wherein the L×N sensor capacitors of each of the X rows are respectively connected to the L×N receiving terminals, respectively,

wherein the transmitter circuitry is configured to sequentially transmit the drive signals to each of the X rows of sensor capacitors from the X transmitting terminals, and

wherein the multiplexer is configured to sequentially forwards N sense signals supplied to N receiving terminals of each of the L sets of receiving terminals to the N receiver circuitries.

Assignments (2)
SECURITY INTEREST Recorded Feb 14, 2020
From: SYNAPTICS INCORPORATED
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 051936/0103 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 20, 2017
From: TANAKA, NOBUKAZU; NOTO, TAKAYUKI; TANEMURA, TETSUO
To: SYNAPTICS INCORPORATED
Reel/Frame 043912/0768 →
Priority Claims (1)
JP 2016-208653 · Oct 25, 2016 · national
Continuity (1)
Related Publication 20180113534A1 · Apr 26, 2018