IP Library Granted Patent US 10,110,319
Granted Patent B1
US 10,110,319 · App. 15/792,396 · Granted Oct 23, 2018

Tap stabilizer method and structure for coherent optical receiver

Inventors: Mario R. Hueda (Córdoba, AR); Oscar E. Agazzi (Irvine, CA)
Assignee: INPHI CORPORATION
H04B10/6161H04L7/0075H04L25/03019H04L27/2634
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,110,319
App. No.
15/792,396
Granted
Oct 23, 2018
Kind
B1
Abstract

A method and structure for a coherent optical receiver device. Timing recovery (TR) is implemented after channel dispersion (i.e., chromatic dispersion (CD) and polarization mode dispersion (PMD)) compensation blocks. This architecture provides both improves performance and reduces power consumption of the device. Also, a TR loop is provided, enabling computing, by an error evaluation module, a first sampling phase error (SPE) and computing, by a timing phase information (TPI) module coupled to the error evaluation module, a second SPE from a plurality of CD equalizer taps PMD equalizer taps. The first and second SPE are combined into a total phase error (TPE) in a combining module, and the resulting TPE is filtered by a timing recovery (TR) filter coupled to an interpolated timing recovery (ITR) module and the combining module. The ITR module then synchronizes an input signal of the coherent optical receiver according to the TPE.

Claims (606)

1. A coherent optical receiver device, the device comprising:

an input signal;

a first fast Fourier transform (FFT) module receiving the input signal, the first FFT module being configured to compute a first discrete Fourier transform (DFT) of the input signal;

a chromatic dispersion (CD) equalizer module coupled to the first FFT module, the CD equalizer module being configured to compensate for CD affecting the input signal;

a polarization mode dispersion (PMD) equalizer module coupled to the CD equalizer and a least means square (LMS) module, the PMD equalizer module having a plurality of PMD taps and being configured to compensate for PMD affecting the input signal following compensation by the CD equalizer module;

an inverse FFT (IFFT) module coupled to the PMD equalizer module, the IFFT module being configured to compute an inverse DFT of the input signal;

an interpolated timing recovery (ITR) module coupled to the IFFT module,

an error evaluation module coupled to the IFFT module, the error evaluation module being configured to compute a first sampling phase error (SPE);

a timing phase information (TPI) module coupled to the error evaluation module and the IFFT module, the TPI module being configured to compute a second SPE from the plurality PMD taps;

a combining module coupled to the TPI module and the error evaluation module, the combining module being configured to combine the first and second SPE into a total phase error (TPE);

a timing recovery (TR) filter coupled to the ITR module and the combining module, the TR filter being configured to filter the TPE;

wherein the ITR module is configured to synchronize the input signal using the TPE; and

a second FFT module coupled to the error evaluation module, the second FFT module being configured to compute a second DFT of the input signal;

wherein the LMS module is coupled to the second FFT module, the CD equalizer module, and the PMD equalizer module, the LMS module being configured to filter the input signal.

2. The device of claim 1 wherein the input signal is a dual-polarization input with an x-type polarization input and a y-type polarization input.

3. The device of claim 1 wherein the CD equalizer module includes a non-adaptive frequency-domain (FD) equalizer, and wherein the PMD equalizer module includes an adaptive FD equalizer.

4. The device of claim 1 wherein the first SPE is computed according to a baud rate synchronization technique based on a Muller and Mueller phase error.

5. The device of claim 1 wherein the first SPE is computed according to the following equation:

ɛ

m

m

=

K

m

m

(

nN

p

+

2

(

n

+

1

)

N

p

a

^

*

(

k

)

q

(

k

-

1

)

-

a

^

*

(

k

-

1

)

q

(

k

)

)

where K mm is a certain gain,

where refers to real component of a complex number,

where N p is a parallelism factor,

where q(k) is an input of slicer and error evaluation module, and

where â* is an output of the slicer and error evaluation module.

6. The device of claim 1 wherein the second SPE is computed from the plurality of PMD taps according to the following equation:

ε fse =−K fse angle( det ( M f ))

where K fse =[2 −1 , . . . , 2 −4 ], and

where M f =e −j2ω 0 τ |P(ω 0 )| 2 Z(ω 0 , −ω 0 , t),

where ω 0 is a given frequency,

where

τ

=

Δ

T

(

T

+

Δ

T

)

t

<

200

x

10

-

6

t

,

where P(ω 0 ) is a CD parameter, and

where Z(ω 0 , −ω 0 , t) is a unitary matrix for all (ω 0 , t).

7. The device of claim 1 wherein the second SPE is computed from the plurality of PMD taps according to the following equation:

ε fse =2ω 0 τ

where ω 0 is a given frequency, and

where

τ

=

Δ

T

(

T

+

Δ

T

)

t

<

200

x

10

-

6

t

,

where t is a given time, and

where T is a symbol period.

8. The device of claim 1 wherein the error evaluation module includes a slicer module configured to derive a data stream from the input signal.

9. The device of claim 1 further comprising a zero padding module coupled to between the error evaluation module and the second FFT module, the zero padding module being configured to increase a sampling rate of the input signal.

10. A method of operating a coherent optical receiver device, the method comprising:

providing an input signal;

computing, by a first fast Fourier transform (FFT) module receiving the input signal, a first discrete Fourier transform (DFT) of the input signal;

compensating, by a chromatic dispersion (CD) equalizer module coupled to the first FFT module, for CD affecting the input signal;

compensating, by a polarization mode dispersion (PMD) equalizer module coupled to the CD equalizer module and coupled to a least means square (LMS) module and having a plurality of PMD taps, for PMD affecting the input signal following the compensation by the CD equalizer module;

computing, by an inverse FFT (IFFT) module coupled to the PMD equalizer module, an inverse DFT of the input signal;

computing, by an error evaluation module coupled to the IFFT module, a first sampling phase error (SPE);

computing, by a timing phase information (TPI) module coupled to the error evaluation module and the IFFT module, a second SPE from the plurality of PMD taps;

combining, by a combining module coupled to the TPI module and the error evaluation module, the first and second SPE into a total phase error (TPE);

filtering, by a timing recovery (TR) filter coupled to an interpolated timing recovery (ITR) module and the combining module, the TPE;

synchronizing, by the ITR module, the input signal according to the TPE;

computing, by a second FFT module coupled to the error evaluation module, a second DFT of the input signal; and

filtering, by the LMS module coupled to the CD equalizer module and the second FFT module and the PMD equalizer module, the input signal.

11. The method of claim 10 wherein the input signal is a dual-polarization input with an x-type polarization input and a y-type polarization input.

12. The method of claim 10 wherein compensating by the CD equalizer module includes compensating by a non-adaptive frequency-domain (FD) equalizer, and wherein compensating by the PMD equalizer module includes compensating by an adaptive FD equalizer.

13. The method of claim 10 wherein the first SPE is computed according to a baud rate synchronization technique based on a Muller and Mueller phase error.

14. The method of claim 10 wherein the first SPE is computed according to the following equation:

ɛ

m

m

=

K

m

m

(

nN

p

+

2

(

n

+

1

)

N

p

a

^

*

(

k

)

q

(

k

-

1

)

-

a

^

*

(

k

-

1

)

q

(

k

)

)

where K mm is a certain gain,

where refers to real component of a complex number,

where N p is a parallelism factor,

where q(k) is an input of slicer and error evaluation module, and

where â* is an output of the slicer and error evaluation module.

15. The device of claim 10 wherein the second SPE is computed from the plurality of PMD taps according to the following equation:

ε fse =−K fse angle( det ( M f ))

where K fse =[2 −1 , . . . , 2 −4 ], and

where M f =e −j2ω 0 τ |P(ω 0 )| 2 Z(ω 0 , −ω 0 , t),

where ω 0 is a given frequency,

where

τ

=

Δ

T

(

T

+

Δ

T

)

t

<

200

x

10

-

6

t

,

where P(ω 0 ) is a CD parameter, and

where Z(ω 0 , −ω 0 , t) is a unitary matrix for all (ω 0 , t).

16. The device of claim 10 wherein the second SPE is computed from the plurality of PMD taps according to the following equation:

ε fse =2ω 0 τ

where ω 0 is a given frequency, and

where

τ

=

Δ

T

(

T

+

Δ

T

)

t

<

200

x

10

-

6

t

,

where t is a given time, and

where T is a symbol period.

17. The method of claim 10 further comprising deriving, by a slicer module configured with the error evaluation module, a data stream from the input signal.

18. The method of claim 10 further comprising increasing, by a zero padding module coupled between the error evaluation module and the second FFT, a sampling rate of the input signal.

19. An error compensation device configured within a coherent optical receiver, the device comprising:

an input signal;

a chromatic dispersion (CD) equalizer module being configured to compensate for CD affecting the input signal;

a polarization mode dispersion (PMD) equalizer module coupled to the CD equalizer and a least means square (LMS) module, the PMD equalizer module having a plurality of PMD taps and being configured to compensate for PMD affecting the input signal following compensation by the CD equalizer module;

an error evaluation module coupled to the PMD equalizer module, the error evaluation module being configured to compute a first sampling phase error (SPE);

a timing phase information (TPI) module coupled to the error evaluation module and the PMD equalizer module, the TPI module being configured to compute a second SPE from the plurality PMD taps;

a combining module coupled to the TPI module and the error evaluation module, the combining module being configured to combine the first and second SPE into a total phase error (TPE);

a timing recovery (TR) filter coupled to the combining module, the TR filter being configured to filter the TPE; and

an interpolated timing recovery (ITR) module coupled to the combining module and the PMD equalizer module, the ITR module being configured to synchronize the input signal using the TPE;

wherein the LMS module is coupled to the error evaluation module, the CD equalizer module, and the PMD equalizer module, the LMS module being configured to filter the input signal.

20. The device of claim 19 wherein the input signal is a dual-polarization input with an x-type polarization input and a y-type polarization input.

21. The device of claim 19 wherein the CD equalizer module includes a non-adaptive frequency-domain (FD) equalizer, and wherein the PMD equalizer module includes an adaptive FD equalizer.

22. The device of claim 19 wherein the first SPE is computed according to a baud rate synchronization technique based on a Muller and Mueller phase error.

23. The device of claim 19 wherein the first SPE is computed according to the following equation:

ɛ

m

m

=

K

m

m

(

nN

p

+

2

(

n

+

1

)

N

p

a

^

*

(

k

)

q

(

k

-

1

)

-

a

^

*

(

k

-

1

)

q

(

k

)

)

where K mm is a certain gain,

where refers to real component of a complex number,

where N p is a parallelism factor,

where q(k) is an input of slicer and error evaluation module, and

where â* is an output of the slicer and error evaluation module.

24. The device of claim 19 wherein the second SPE is computed from the plurality of PMD taps according to the following equation:

ε fse =−K fse angle( det ( M f ))

where K fse =[2 −1 , . . . , 2 −4 ], and

where M f =e −j2ω 0 τ |P(ω 0 )| 2 Z(ω 0 , −ω 0 , t),

where ω 0 is a given frequency,

where

τ

=

Δ

T

(

T

+

Δ

T

)

t

<

200

x

10

-

6

t

,

where P(ω 0 ) is a CD parameter, and

where Z(ω 0 , −ω 0 , t) is a unitary matrix for all (ω 0 , t).

25. The device of claim 19 wherein the second SPE is computed from the plurality of PMD taps according to the following equation:

ε fse =2ω 0 τ

where ω 0 is a given frequency, and

where

τ

=

Δ

T

(

T

+

Δ

T

)

t

<

200

x

10

-

6

t

,

where t is a given time, and

where T is a symbol period.

26. A method of error compensation for a coherent optical receiver device, the method comprising:

providing an input signal;

compensating, by a chromatic dispersion (CD), for CD affecting the input signal;

compensating, by a polarization mode dispersion (PMD) equalizer module coupled to the CD equalizer module and coupled to a least means square (LMS) module and having a plurality of PMD taps, for PMD affecting the input signal following the compensation by the CD equalizer module;

computing, by an error evaluation module coupled to the PMD equalizer module, a first sampling phase error (SPE);

computing, by a timing phase information (TPI) module coupled to the error evaluation module, a second SPE from the plurality of PMD taps;

combining, by a combining module coupled to the TPI module and the error evaluation module, the first and second SPE into a total phase error (TPE);

filtering, by a timing recovery (TR) filter coupled to an interpolated timing recovery (ITR) module and the combining module, the TPE;

synchronizing, by an ITR module coupled to the PMD equalizer module, the input signal according to the TPE; and

filtering, by the LMS module, the input signal.

27. The method of claim 26 wherein the input signal is a dual-polarization input with an x-type polarization input and a y-type polarization input.

28. The method of claim 26 wherein the first SPE is computed according to a baud rate synchronization technique based on a Muller and Mueller phase error.

29. The method of claim 26 wherein the first SPE is computed according to the following equation:

ɛ

m

m

=

K

m

m

(

nN

p

+

2

(

n

+

1

)

N

p

a

^

*

(

k

)

q

(

k

-

1

)

-

a

^

*

(

k

-

1

)

q

(

k

)

)

where K mm is a certain gain

where refers to real component of a complex number

where N p is a parallelism factor,

where q(k) is an input of slicer and error evaluation module, and

where â* is an output of the slicer and error evaluation module.

30. The device of claim 26 wherein the second SPE is computed from the plurality of PMD taps according to the following equation:

ε fse =−K fse angle( det ( M f ))

where K fse =[2 −1 , . . . , 2 −4 ], and

where M f =e −j2ω 0 τ |P(ω 0 )| 2 Z(ω 0 , −ω 0 , t),

where ω 0 is a given frequency,

where

τ

=

Δ

T

(

T

+

Δ

T

)

t

<

200

x

10

-

6

t

,

where P(ω 0 ) is a CD parameter, and

where Z(ω 0 , −ω 0 , t) is a unitary matrix for all (ω 0 , t).

31. The device of claim 26 wherein the second SPE is computed from the plurality of PMD taps according to the following equation:

ε fse =2ω 0 τ

where ω 0 is a given frequency, and

where

τ

=

Δ

T

(

T

+

Δ

T

)

t

<

200

x

10

-

6

t

,

where t is a given time, and

where T is a symbol period.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2021
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE LTD.
Reel/Frame 057336/0873 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2021
From: MARVELL TECHNOLOGY CAYMAN I
To: CAVIUM INTERNATIONAL
Reel/Frame 057279/0519 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2021
From: INPHI CORPORATION
To: MARVELL TECHNOLOGY CAYMAN I
Reel/Frame 056649/0823 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2017
From: HUEDA, MARIO R.; AGAZZI, OSCAR E.
To: INPHI CORPORATION
Reel/Frame 044011/0866 →
Continuity (7)
Provisional Application 62412047 · Oct 24, 2016
Provisional Application 62412039 · Oct 24, 2016
Provisional Application 62412015 · Oct 24, 2016
Provisional Application 62412002 · Oct 24, 2016
Provisional Application 62412033 · Oct 24, 2016
Provisional Application 62412052 · Oct 24, 2016
Provisional Application 62412071 · Oct 24, 2016