IP Library Granted Patent US 10,810,123
Granted Patent B1
US 10,810,123 · App. 15/792,888 · Granted Oct 20, 2020

Flush strategy for using DRAM as cache media system and method

Inventors: Xinlei Xu (Beijing, CN); Jian Gao (Beijing, CN); Lifeng Yang (Beijing, CN); Michael P. Wahl (Bulverde, TX)
Assignee: EMC IP Holding Company, LLC
G06F12/0804G06F12/0882G06F13/1636G06F13/28G06F2212/7201
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Quick Facts
Patent No.
US 10,810,123
App. No.
15/792,888
Granted
Oct 20, 2020
Kind
B1
Abstract

A method, computer program product, and computer system for receiving, by a computing device, an I/O request. The I/O request may be processed as a write miss I/O. One or more dirty pages associated with the write miss I/O may be placed into a tree according to a key. It may be determined whether one of a first event and a second event occurs. A data flush may be triggered for the tree when the first event occurs, and the data flush may be triggered for the data flush for the tree when the second event occurs.

Claims (47)

1. A computer-implemented method comprising:

receiving, by a computing device, an I/O request;

processing the I/O request as a write miss I/O, wherein processing the I/O request as a write miss I/O includes searching a hash table;

allocating at least one free cache page from a cache free page queue;

transferring data associated with the write miss I/O into a dynamic random access memory;

writing one or more dirty pages associated with the write miss I/O to a first non-volatile memory express device and a second non-volatile memory express device, wherein the first non-volatile memory device and second non-volatile memory device are two different devices;

updating a status of the at least one free cache page, wherein updating a status of the at least one free cache page includes inserting the one or more dirty pages associated with the write miss I/O into the hash table;

placing the one or more dirty pages associated with the write miss I/O into a tree according to a key;

determining whether one of a first event and a second event occurs; and

triggering a data flush for the tree when the first event occurs, and triggering the data flush for the tree when the second event occurs.

2. The computer-implemented method of claim 1 wherein the tree includes a red-black tree.

3. The computer-implemented method of claim 2 wherein a leaf of the red-black tree is a set of the one or more dirty pages.

4. The computer-implemented method of claim 3 wherein the key of the red-black tree includes content associated with a logical unit number and a logical block address.

5. The computer-implemented method of claim 1 wherein the first event includes a node of the tree being completely filled with dirty pages.

6. The computer-implemented method of claim 1 wherein the second event includes reaching a threshold amount of free pages in a cache.

7. The computer-implemented method of claim 6 further comprising combining two nodes in the tree that have sequential logical block addresses for the data flush.

8. A computer program product residing on a non-transitory computer readable storage medium having a plurality of instructions stored thereon which, when executed across one or more processors, causes at least a portion of the one or more processors to perform operations comprising:

receiving, by a computing device, an I/O request;

processing the I/O request as a write miss I/O, wherein processing the I/O request as a write miss I/O includes searching a hash table;

allocating at least one free cache page from a cache free page queue;

transferring data associated with the write miss I/O into a dynamic random access memory;

writing one or more dirty pages associated with the write miss I/O to a first non-volatile memory express device and a second non-volatile memory express device, wherein the first non-volatile memory device and second non-volatile memory device are two different devices;

updating a status of the at least one free cache page, wherein updating a status of the at least one free cache page includes inserting the one or more dirty pages associated with the write miss I/O into the hash table;

placing the one or more dirty pages associated with the write miss I/O into a tree according to a key;

determining whether one of a first event and a second event occurs; and

triggering a data flush for the tree when the first event occurs, and triggering the data flush for the tree when the second event occurs.

9. The computer program product of claim 8 wherein the tree includes a red-black tree.

10. The computer program product of claim 9 wherein a leaf of the red-black tree is a set of the one or more dirty pages.

11. The computer program product of claim 10 wherein the key of the red-black tree includes content associated with a logical unit number and a logical block address.

12. The computer program product of claim 8 wherein the first event includes a node of the tree being completely filled with dirty pages.

13. The computer program product of claim 8 wherein the second event includes reaching a threshold amount of free pages in a cache.

14. The computer program product of claim 13 wherein the operations further comprise combining two nodes in the tree that have sequential logical block addresses for the data flush.

15. A computing system including one or more processors and one or more memories configured to perform operations comprising:

receiving, by a computing device, an I/O request;

processing the I/O request as a write miss I/O, wherein processing the I/O request as a write miss I/O includes searching a hash table;

allocating at least one free cache page from a cache free page queue;

transferring data associated with the write miss I/O into a dynamic random access memory;

writing one or more dirty pages associated with the write miss I/O to a first non-volatile memory express device and a second non-volatile memory express device, wherein the first non-volatile memory device and second non-volatile memory device are two different devices;

updating a status of the at least one free cache page, wherein updating a status of the at least one free cache page includes inserting the one or more dirty pages associated with the write miss I/O into the hash table;

placing the one or more dirty pages associated with the write miss I/O into a tree according to a key;

determining whether one of a first event and a second event occurs; and

triggering a data flush for the tree when the first event occurs, and triggering the data flush for the tree when the second event occurs.

16. The computing system of claim 15 wherein the tree includes a red-black tree.

17. The computing system of claim 16 wherein a leaf of the red-black tree is a set of the one or more dirty pages.

18. The computing system of claim 17 wherein the key of the red-black tree includes content associated with a logical unit number and a logical block address.

19. The computing system of claim 15 wherein the first event includes a node of the tree being completely filled with dirty pages and wherein the second event includes reaching a threshold amount of free pages in a cache.

20. The computing system of claim 19 wherein the operations further comprise combining two nodes in the tree that have sequential logical block addresses for the data flush.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
SECURITY AGREEMENT Recorded Oct 1, 2021
From: DELL PRODUCTS, L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 057682/0830 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 30, 2017
From: XU, XINLEI; GAO, JIAN; YANG, LIFENG; WAHL, MICHAEL P
To: EMC IP HOLDING COMPANY, LLC
Reel/Frame 043981/0334 →
Cited By (3)
US 12,248,706 US 12,353,747 US 12,423,231