IP Library Granted Patent US 10,050,614
Granted Patent B2
US 10,050,614 · App. 15/793,581 · Granted Aug 14, 2018

Method and system for reliable bootstrapping switches

Inventors: Yongjian Tang (Carlsbad, CA); Xuefeng Chen (Carlsbad, CA)
Assignee: Maxlinear, Inc.
H03K17/063
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Quick Facts
Patent No.
US 10,050,614
App. No.
15/793,581
Granted
Aug 14, 2018
Kind
B2
Abstract

Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor, wherein: source terminals of both a diode-connected transistor and a second MOS transistor are coupled to the gate terminal of the switching MOS transistor; drain terminals of both the diode-connected transistor and the second MOS transistor are coupled to a source terminal of a third MOS transistor, the third MOS transistor coupled in series with a fourth MOS transistor; and a drain terminal of the fourth MOS transistor is coupled to ground. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage to activate the pull-down path.

Claims (36)

1. A method for communication, the method comprising:

sampling a received signal with a switch, said switch comprising:

a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor, wherein:

first terminals of both a diode-connected transistor and a second MOS transistor are coupled to the gate terminal of the switching MOS transistor;

second terminals of both the diode-connected transistor and the second MOS transistor are coupled to a first terminal of a third MOS transistor, a second terminal of the third MOS transistor is coupled to a first terminal of a fourth MOS transistor; and

a second terminal of the fourth MOS transistor is coupled to ground.

2. The method according to claim 1 , wherein the third and fourth MOS transistors are in series with the second MOS transistor.

3. The method according to claim 1 , comprising switching a gate terminal of the fourth transistor from ground to a supply voltage, VDD, to activate the pull-down path.

4. The method according to claim 1 , comprising coupling a capacitor between gate and source terminals of the switching MOS transistor to switch said switching MOS transistor to an ON state.

5. The method according to claim 4 , comprising coupling said capacitor to ground and a supply voltage to switch said switching MOS transistor to an OFF state.

6. The method according to claim 5 , comprising configuring said fourth MOS transistor in an OFF state for switching said switching MOS transistor to said ON state.

7. The method according to claim 1 , comprising protecting MOS transistors in said pull-down path from voltages with a magnitude above a supply voltage for said bootstrapping switch utilizing said diode-connected MOS transistor.

8. The method according to claim 1 , wherein said bootstrapping switch samples analog signals in an analog-to-digital converter (ADC).

9. The method according to claim 1 , wherein the bootstrapping switch is integrated on a complementary metal-oxide semiconductor (CMOS) chip.

10. The method according to claim 1 , wherein the bootstrapping switch comprises NMOS transistors.

11. A system for communication, the system comprising:

one or more circuits comprising a switch, said switch comprising:

a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor, wherein:

first terminals of both a diode-connected transistor and a second MOS transistor are coupled to the gate terminal of the switching MOS transistor;

second terminals of both the diode-connected transistor and the second MOS transistor are coupled to a first terminal of a third MOS transistor, a second terminal of the third MOS transistor is coupled to a first terminal of a fourth MOS transistor; and

a second terminal of the fourth MOS transistor is coupled to ground.

12. The system according to claim 11 , wherein the third and fourth MOS transistors are in series with the second MOS transistor.

13. The system according to claim 11 , wherein said one or more circuits are operable to switch a gate terminal of the fourth transistor from ground to a supply voltage, VDD, to activate the pull-down path.

14. The system according to claim 11 , wherein said one or more circuits are operable to couple a capacitor between gate and source terminals of the switching MOS transistor to switch said switching MOS transistor to an ON state.

15. The system according to claim 14 , wherein said one or more circuits are operable to couple said capacitor to ground and a supply voltage to switch said switching MOS transistor to an OFF state.

16. The system according to claim 15 , wherein said one or more circuits are operable to configure said fourth MOS transistor in an OFF state for switching said switching MOS transistor to said ON state.

17. The system according to claim 11 , wherein said one or more circuits are operable to protect MOS transistors in said pull-down path from voltages with a magnitude above a supply voltage for said bootstrapping switch utilizing said diode-connected MOS transistor.

18. The system according to claim 11 , wherein said one or more circuits are operable to sample analog signals utilizing said bootstrapping switch in an analog-to-digital converter (ADC).

19. The system according to claim 11 , wherein the one or more circuits comprises a complementary metal-oxide semiconductor (CMOS) chip.

20. A system for communication, the system comprising:

one or more circuits comprising a switching metal-oxide semiconductor (MOS) transistor having a pull-down path, said pull-down path comprising:

first terminals of both a diode-connected MOS transistor and a second MOS transistor coupled to the gate terminal of the switching MOS transistor;

a first terminal of a third MOS transistor is coupled to a second terminal of the second MOS transistor;

a first terminal of a fourth MOS transistor is coupled to a second terminal of the third MOS transistor;

second terminals of both the diode-connected transistor and the second MOS transistor are coupled to a first terminal of the third MOS transistor; and

a second terminal of the fourth MOS transistor is coupled to ground.

Assignments (5)
SECURITY AGREEMENT Recorded Jul 9, 2021
From: MAXLINEAR, INC.; MAXLINEAR COMMUNICATIONS, LLC; EXAR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 056816/0089 →
RELEASE OF SECURITY INTEREST Recorded Jun 23, 2021
From: MUFG UNION BANK, N.A.
To: MAXLINEAR, INC.; EXAR CORPORATION; MAXLINEAR COMMUNICATIONS LLC
Reel/Frame 056656/0204 →
SUCCESSION OF AGENCY (REEL 052777 / FRAME 0216) Recorded Jul 1, 2020
From: JPMORGAN CHASE BANK, N.A.
To: MUFG UNION BANK, N.A.
Reel/Frame 053116/0418 →
SECURITY AGREEMENT Recorded May 28, 2020
From: MAXLINEAR, INC.; ENTROPIC COMMUNICATIONS, LLC; EXAR CORPORATION
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 052777/0216 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2018
From: TANG, YONGJIAN; CHEN, XUEFENG
To: MAXLINEAR, INC.
Reel/Frame 046347/0493 →
Continuity (4)
Continuation 15444662 · Feb 28, 2017
Continuation 14585707 · Dec 30, 2014
Provisional Application 61921971 · Dec 30, 2013
Related Publication 20180048301A1 · Feb 15, 2018