IP Library Granted Patent US 10,608,750
Granted Patent B2
US 10,608,750 · App. 15/797,664 · Granted Mar 31, 2020

Method and system for a narrowband, non-linear optoelectronic receiver

Inventor: John Andrew Guckenberger (San Diego, CA)
Assignee: Luxtera, Inc.
H04B10/6931H04B10/2575H04B10/60H04B10/66H04B10/69H04B10/6972
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Quick Facts
Patent No.
US 10,608,750
App. No.
15/797,664
Granted
Mar 31, 2020
Kind
B2
Abstract

Methods and systems for a narrowband, non-linear optoelectronic receiver are disclosed and may include amplifying a received signal, limiting a bandwidth of the received signal, and restoring the signal utilizing a level restorer, which may include a non-return to zero (NRZ) level restorer. The NRZ level restorer may include a pulse-triggered bistable circuit, which may include two parallel inverters, with one being a feedback path for the other. The inverters may be single-ended or differential. A photogenerated signal may be amplified in the receiver utilizing a transimpedance amplifier and programmable gain amplifiers (PGAs). A received electrical signal may be amplified via PGAs. The bandwidth of the received signal may be limited utilizing one or more of: a low pass filter, a bandpass filter, a high pass filter, a differentiator, or a series capacitance on the chip. The signal may be received from a photodiode integrated on the chip.

Claims (31)

1. A method for processing signals, the method comprising:

in a receiver on a chip,

amplifying a received signal utilizing a transimpedance amplifier and one or more variable gain amplifiers (VGAs);

limiting a bandwidth of said received signal utilizing a band pass filter; and

restoring said received signal to a non-return to zero (NRZ) signal using a level restorer comprising a pulse-triggered bistable circuit.

2. The method according to claim 1 , comprising limiting the bandwidth to be centered around a frequency of 5 GHz.

3. The method according to claim 1 , wherein said chip comprises a complementary metal-oxide semiconductor (CMOS) chip.

4. The method according to claim 1 , wherein said pulse-triggered bistable circuit comprises parallel single-ended inverters.

5. The method according to claim 1 , wherein said pulse-triggered bistable circuit comprises parallel differential inverters.

6. The method according to claim 1 , comprising amplifying a received electrical signal via one or more VGAs.

7. The method according to claim 1 , comprising limiting said bandwidth of said received signal utilizing one or more of: a differentiator or a series capacitance on said chip.

8. The method according to claim 1 , comprising receiving said signal from a photodiode integrated on said chip.

9. The method according to claim 8 , wherein said photodiode is AC coupled to an amplifier for said amplifying.

10. A system for processing signals, the system comprising:

in a receiver on a chip, one or more circuits operable to amplify a received signal utilizing a transimpedance amplifier and one or more variable gain amplifiers (VGAs);

said one or more circuits comprise a band pass filter; and

said one or more circuits restore said received signal to a Non-return to Zero (NRZ) signal using a level restorer comprising a pulse-triggered bistable circuit.

11. The system according to claim 10 , wherein said one or more circuits are operable to limit the bandwidth to be centered around a frequency of 5 GHz.

12. The system according to claim 10 , wherein said chip comprises a complementary metal-oxide semiconductor (CMOS) chip.

13. The system according to claim 10 , wherein said pulse-triggered bistable circuit comprises parallel single-ended inverters.

14. The system according to claim 10 , wherein said pulse-triggered bistable circuit comprises parallel differential inverters.

15. The system according to claim 10 , wherein said one or more circuits are enabled to amplify a received electrical signal via one or more VGAs.

16. The system according to claim 10 , wherein said one or more circuits are enabled to limit said bandwidth of said received signal utilizing one or more of: a differentiator or a series capacitance on said chip.

17. The system according to claim 10 , wherein said one or more circuits are enabled to receive said signal from a photodiode integrated on said chip.

18. A system for processing signals, the system comprising:

in a receiver on a chip, one or more circuits that are operable to:

receive an electrical signal;

AC couple the electrical signal to an amplifier;

amplify the AC coupled electrical signal utilizing a transimpedance amplifier and one or more variable gain amplifiers (VGAs);

limit a bandwidth of the amplified signals; and

restore said received signal to a Non-return to Zero (NRZ) signal using a level restorer comprising a pulse-triggered bistable circuit.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNOR'S NAME PREVIOUSLY RECORDED AT REEL: 058979 FRAME: 0027. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 24, 2022
From: LUXTERA LLC
To: CISCO TECHNOLOGY, INC.
Reel/Frame 059496/0803 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2022
From: CISCO SYSTEMS, INC.
To: CISCO TECHNOLOGY, INC.
Reel/Frame 058979/0027 →
CHANGE OF NAME Recorded Feb 6, 2020
From: LUXTERA, INC.
To: LUXTERA LLC
Reel/Frame 052019/0811 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 3, 2019
From: GUCKENBERGER, JOHN ANDREW
To: LUXTERA, INC.
Reel/Frame 049072/0860 →