IP Library Granted Patent US 10,319,428
Granted Patent B2
US 10,319,428 · App. 15/798,995 · Granted Jun 11, 2019

Control method of solid state storage device

Inventors: Shih-Jia Zeng (Taipei, TW); Jen-Chien Fu (Taipei, TW); Tsu-Han Lu (Taipei, TW); Kuan-Chun Chen (Taipei, TW)
Assignee: LITE-ON TECHNOLOGY CORPORATION
G11C11/40615G11C11/4091G11C16/14
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,319,428
App. No.
15/798,995
Granted
Jun 11, 2019
Kind
B2
Abstract

A control method of a solid state storage device includes the following steps. Firstly, a block of a memory cell array is checked. Then, a judging step is performed to judge whether a data storage time period of the block exceeds a threshold period. If the data storage time period of the block exceeds the threshold period, the block is tagged or a data of the block is refreshed.

Claims (13)

1. A control method for refreshing a solid state storage device, the control method comprising steps of:

checking a block of a memory cell array;

judging whether a data storage time period of the block exceeds a threshold period, wherein said data storage time is an age of data storage on the block before refreshing;

if the data storage time period of the block exceeds the threshold period, then tagging the block or refreshing a data of the block;

if the data storage time period of the block does not exceed the threshold period and a program erase count of the block exceeds a threshold count value, then acquiring a block information and an environment information, and predicting a possibility of read retry in the next few days according to the block information and the environment information; and

if the possibility of read retry in the next few days is higher than a threshold possibility value, then tagging the block or refreshing the data of the block.

2. The control method as claimed in claim 1 , wherein an interface controller of the solid state storage device periodically checks the block of the memory cell array at a predetermined time interval.

3. The control method as claimed in claim 1 , wherein the tagged block is read, an interface controller of the solid state storage device acquires a read data according to a read retry voltage set.

4. The control method as claimed in claim 1 , wherein while the data of the block is refreshed, the data stored in the block is moved to a blank block of the memory cell array.

5. The control method as claimed in claim 1 , wherein after the block information and the environment information are inputted into a prediction model, the possibility of read retry in the next few days is outputted from the prediction model.

6. The control method as claimed in claim 5 , wherein the prediction model is a prediction function or a look-up table.

7. The control method as claimed in claim 5 , wherein the block information includes a data storage time period, a program time, an erase time, an error bit, a current possibility of read retry, a program count, an erase count or a read count.

8. The control method as claimed in claim 5 , wherein the environment information includes a current operation temperature or a previous operation temperature.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2019
From: LITE-ON TECHNOLOGY CORPORATION
To: SOLID STATE STORAGE TECHNOLOGY CORPORATION
Reel/Frame 051213/0875 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 31, 2017
From: ZENG, SHIH-JIA; FU, JEN-CHIEN; LU, TSU-HAN; CHEN, KUAN-CHUN
To: LITE-ON TECHNOLOGY CORPORATION
Reel/Frame 043993/0394 →
Priority Claims (1)
CN 2017 1 0676223 · Aug 9, 2017 · national
Continuity (1)
Related Publication 20190051346A1 · Feb 14, 2019