Managing latency and power in a heterogeneous distributed biometric authentication hardware

1. A method of managing latency and power in a biometric authentication system, comprising:

receiving a biometric image information on a first processor and a second processor, wherein a processing capability of the first processor is greater than the processing capability of the second processor;

configuring the first processor to operate in a high speed mode;

determining a feature extraction result and a feature matching result with the first processor operating in the high speed mode, wherein the feature matching result is based on a comparison of the received biometric image information and a previously stored biometric template;

providing the feature extraction result and the feature matching result to the second processor;

configuring the first processor to operate in a default mode, wherein the processing capability of the first processor while in the default mode is less than it is while in the high speed mode; and

determining an authentication score with the second processor, wherein the authentication score is based at least in part on the feature matching result determined on the first processor.

2. The method of claim 1 comprising:

detecting a biometric object within the biometric image information with the first processor when the first processor is in the default mode; and

configuring the first processor to operate in the high speed mode after the biometric object is detected.

3. The method of claim 2 wherein the biometric object is a fingerprint image.

4. The method of claim 2 wherein the biometric object is an iris image.

5. The method of claim 1 comprising:

detecting a temporal change in the biometric image information with the first processor when the first processor is in the default mode; and

configuring the first processor to operate in the high speed mode after the temporal change in the biometric image information is detected.

6. The method of claim 1 further comprising:

determining a liveness score with the first processor when the first processor is in the high speed mode; and

providing the liveness score to the second processor.

7. The method of claim 6 wherein determining the authentication score with the second processor is based at least in part on the liveness score determined on the first processor.

8. The method of claim 1 wherein the second processor is activated on or about a time the feature extraction result and the feature matching result are provided to the second processor, and deactivated on or about a time after the authentication score is determined.

9. The method of claim 1 wherein a power consumption of the first processor while in the default mode is less than it is while in the high speed mode.

10. A system for managing latency and power in a biometric authentication system, comprising:

at least one application processor operating in a default mode and configured to:

receive a biometric image information;

operate in a high speed mode to determine a feature extraction result and feature matching result, wherein the feature matching result is based on a comparison of the received biometric image information and a previously stored biometric template, and a processing capability of the at least one application processor while in the high speed mode is greater than it is while in the default mode;

a secure processor operably coupled to the at least one application processor and configured to:

receive the biometric image information;

receive the feature extraction result from the at least one application processor;

determine an authentication score based at least in part on the feature matching result determined on the at least one application processor,

wherein the at least one application processor and the secure processor comprise hardware processors.

11. The system of claim 10 wherein the at least one application processor is further configured to detect a biometric object within the biometric image information when operating in the default mode and then operate in the high speed mode after the biometric object is detected.

12. The system of claim 11 wherein the biometric object is a fingerprint image.

13. The system of claim 11 wherein the biometric object is an iris image.

14. The system of claim 10 wherein the at least one application processor is further configured to detect a temporal change in the biometric image information when operating in the default mode and then operate in the high speed mode after the temporal change in the biometric image information is detected.

15. The system of claim 10 wherein the at least one application processor is further configured to:

determine a liveness score when operating in the high speed mode; and

provide the liveness score to the secure processor.

16. The system of claim 15 wherein the secure processor is further configured to determine the authentication score based at least in part on the liveness score determined on the at least one application processor.

17. The system of claim 10 wherein the secure processor is activated on or about a time the feature extraction result and the feature matching result are received from the at least on application processor, and deactivated on or about a time after the authentication score is determined.

18. The system of claim 10 wherein a power consumption of the at least one application processor while in the default mode is less than it is while in the high speed mode.

19. A system for managing latency and power in a biometric authentication system, comprising:

means for receiving a biometric image information on a first processor and a second processor, wherein a processing capability of the first processor is greater than the processing capability of the second processor;

means for configuring the first processor to operate in a high speed mode;

means for determining a feature extraction result and a feature matching result with the first processor operating in the high speed mode, wherein the feature matching result is based on a comparison of the received biometric image information and a previously stored biometric template;

means for providing the feature extraction result and the feature matching result to the second processor;

means for configuring the first processor to operate in a default mode, wherein the processing capability of the first processor while in the default mode is less than it is while in the high speed mode; and

means for determining an authentication score with the second processor, wherein the authentication score is based at least in part on the feature matching result determined on the first processor.

20. The system of claim 19 further comprising:

means for detecting a biometric object within the biometric image information with the first processor when the first processor is in the default mode; and

means for configuring the first processor to operate in the high speed mode after the biometric object is detected.

21. The system of claim 20 wherein the biometric object is a fingerprint image.

22. The system of claim 20 wherein the biometric object is an iris image.

23. The system of claim 19 further comprising:

means for detecting a temporal change in the biometric image information with the first processor when the first processor is in the default mode; and

means for configuring the first processor to operate in the high speed mode after the temporal change in the biometric image information is detected.

24. The system of claim 19 further comprising:

means for determining a liveness score with the first processor when the first processor is in the high speed mode; and

means for providing the liveness score to the second processor.

25. A computer program product, comprising:

a non-transitory computer-readable storage medium comprising:

code for receiving a biometric image information on a first processor and a second processor, wherein a processing capability of the first processor is greater than the processing capability of the second processor;

code for configuring the first processor to operate in a high speed mode;

code for determining a feature extraction result and a feature matching result with the first processor in the high speed mode, wherein the feature matching result is based on a comparison of the received biometric image information and a previously stored biometric template;

code for providing the feature extraction result and the feature matching result to the second processor;

code for configuring the first processor to operate in a default mode, wherein the processing capability of the first processor while in the default mode is less than it is while in the high speed mode; and

code for determining an authentication score with the second processor, wherein the authentication score is based at least in part on the feature matching result determined on the first processor.

26. The computer program product of claim 25 , further comprising:

code for detecting a biometric object within the biometric image information with the first processor when the first processor is in the default mode; and

code for configuring the first processor to operate in the high speed mode after the biometric object is detected.

27. The computer program product of claim 25 , further comprising:

code for detecting a temporal change in the biometric image information with the first processor when the first processor is in the default mode; and

code for configuring the first processor to operate in the high speed mode after the temporal change in the biometric image information is detected.

28. The computer program product of claim 25 , further comprising:

code for determining a liveness score with the first processor when the first processor is in the high speed mode; and

code for providing the liveness score to the second processor.

29. The computer program product of claim 25 wherein the code for providing the feature extraction result and the feature matching result to the second processor includes code for activating the second processor on or about a time the feature extraction result and the feature matching result are provided to the second processor, and code for deactivating the second processor on or about a time after the authentication score is determined.

30. The computer program product of claim 25 wherein the code for configuring the first processor to operate in the default mode decreases a power consumption of the first processor to be less than it is while in the high speed mode.