IP Library Granted Patent US 10,656,338
Granted Patent B2
US 10,656,338 · App. 15/802,009 · Granted May 19, 2020

Wafer-level optoelectronic packaging

Inventor: Yee Loy Lam (Singapore, SG)
Assignee: POET Technologies, Inc.
G02B6/30G02B6/122G02B6/12004G02B6/132G02B6/136G02B6/3652G02B6/423
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Quick Facts
Patent No.
US 10,656,338
App. No.
15/802,009
Granted
May 19, 2020
Kind
B2
Abstract

A wafer-level optoelectronic packaging method includes fabricating a pre-singulated wafer. The pre-singulated wafer has a plurality of sub-mounts. A first sub-mount of the plurality of sub-mounts includes an optical waveguide formed on a substrate, a multi-layered sub-mount boundary wall that is formed on the optical waveguide, and a v-groove that is external to the sub-mount boundary wall. A plurality of optical dies are attached to the corresponding plurality of sub-mounts, such that each optical die is aligned to the optical waveguide of the corresponding sub-mount. A cap-wafer including a plurality of caps is attached to the pre-singulated wafer to obtain an encapsulated pre-singulated wafer. The encapsulated pre-singulated wafer is diced to obtain a plurality of optoelectronic packages. The optical waveguide of each optoelectronic package serves as an interconnection conduit between the corresponding optical die and an optical fiber placed in the corresponding v-groove.

Claims (30)

1. An optoelectronic package, comprising:

a sub-mount comprising:

an optical waveguide formed on top of a substrate; and

a sub-mount boundary wall,

wherein the sub-mount boundary wall comprises a first portion abutting a portion of the optical waveguide,

wherein the first portion of the sub-mount boundary wall and the portion of the optical waveguide comprises a same height,

therein the first portion of the sub-mount boundary wall and the portion of the optical waveguide form an enclosed boundary,

wherein the sub-mount boundary wall comprises a second portion on top of the enclosed boundary,

wherein the second portion comprises

a first dielectric layer formed on top of the enclosed boundary;

a first metal layer formed on top of portions of the first dielectric layer, wherein the first metal layer comprises a wiring trace running across the boundary wall;

a second dielectric layer having a first portion formed on top of the first metal layer and a second portion formed on top of the first dielectric layer; and

a second metal layer formed on top of the second dielectric layer;

an optical die that is attached to the sub-mount and surrounded by the sub-mount boundary wall; and

a cap that is attached to the sub-mount boundary wall to form a cavity for fully enclosing the optical die.

2. The optoelectronic package of claim 1 ,

wherein a first portion of the optical waveguide that lies inside the cavity is aligned with the optical die for receiving an optical signal from the optical die.

3. The optoelectronic package of claim 1 , further comprising:

a third metal layer that is formed on top of a first portion of the wiring trace for electrically connecting to the optical die.

4. The optoelectronic package of claim 1 , further comprising:

a v-groove that is formed by etching the substrate, and external to the sub-mount boundary wall.

5. The optoelectronic package of claim 4 , further comprising:

an optical fiber that is placed in the v-groove, whereby the optical fiber is aligned with a second portion of the optical waveguide that lies outside the cavity for receiving an optical signal from the optical die.

6. The optoelectronic package of claim 5 ,

wherein a top portion of the cap is larger than the surface area of the cavity defined by the boundary wall,

wherein the top portion of the cap has a first opening outside of the surface area that exposes the v-groove for placing the optical fiber in the v-groove.

7. The optoelectronic package of claim 6 ,

wherein the top portion of the cap has a second opening outside of the surface area to expose a first portion of the first metal layer that lies outside the cavity.

8. The optoelectronic package of claim 1 ,

wherein the second metal layer comprises a metal alloy having a melting temperature lower than that of the first metal layer.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME FROM "POET TECHNOLOGIES" TO "POET TECHNOLOGIES, INC" PREVIOUSLY RECORDED AT REEL: 049560 FRAME: 0278 ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Nov 3, 2023
From: DENSELIGHT SEMICONDUCTORS PTE. LTD.
To: POET TECHNOLOGIES, INC.
Reel/Frame 065452/0679 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2019
From: ESPRESSO CAPITAL LTD.
To: OPEL INC.
Reel/Frame 051069/0619 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2019
From: DENSELIGHT SEMICONDUCTORS
To: POET TECHNOLOGIES
Reel/Frame 049560/0278 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 048886 FRAME: 0716. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Apr 19, 2019
From: BB PHOTONICS INC.
To: ESPRESSO CAPITAL LTD.
Reel/Frame 048947/0480 →
SECURITY INTEREST Recorded Apr 15, 2019
From: OPEL INC.
To: ESPRESSO CAPITAL LTD.
Reel/Frame 048886/0716 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2018
From: LAM, YEE LOY
To: DENSELIGHT SEMICONDUCTORS PTE. LTD.
Reel/Frame 046746/0742 →
Continuity (1)
Related Publication 20190129099A1 · May 2, 2019