Method for implementing a reduced size register view data structure in a microprocessor

1. A method of managing a reduced size register view data structure in a processor, the method comprising:

receiving an incoming instruction sequence using a global front end;

grouping instructions from the incoming instruction sequence to form instruction blocks;

populating a register view data structure, wherein the register view data structure stores register information references by the instruction blocks as a set of register templates;

generating a set of snapshots of the register templates to reduce a size of the register view data structure; and

tracking a state of the processor to handle a branch miss-prediction using the register view data structure in accordance with execution of the instruction blocks.

2. The method of claim 1 , wherein the register view data structure, a source view data structure and an instruction view data structure are parts of a scheduler architecture of the processor.

3. The method of claim 1 , further comprising:

determining a last valid register template snapshot in response to branch misprediction.

4. The method of claim 1 , further comprising:

compressing the set of snapshots of the register templates by storing incremental changes between a subset of the set of snapshots.

5. The method of claim 1 , further comprising:

restoring a valid state for the processor by loading a valid register view data structure.

6. The method of claim 5 , wherein the valid register view data structure is reconstructed from a valid register view snapshot.

7. The method of claim 1 , wherein each register template stores inheritance vectors that define dependency and inheritance information referred to by a corresponding instructions block.

8. A processor configured to implement a method of managing a reduced size register view data structure, the processor comprising:

a set of execution units;

a global front end to receive an incoming instruction sequence and to group instructions from the incoming instruction sequence to form instruction blocks; and

a scheduler to schedule execution of the instruction blocks to the set of execution units, the scheduler including a register view data structure, the scheduler to populate a register view data structure, wherein the register view data structure stores register information references by the instruction blocks as a set of register templates, to generate a set of snapshots of the register templates to reduce a size of the register view data structure, and to track a state of the processor to handle a branch miss-prediction using the register view data structure in accordance with execution of the instruction blocks.

9. The processor of claim 8 , wherein the register view data structure, a source view data structure and an instruction view data structure are parts of a scheduler architecture of the processor.

10. The processor of claim 8 , wherein the scheduler is further configured to determine a last valid register template snapshot in response to branch misprediction.

11. The processor of claim 8 , wherein the scheduler is further configured to compress the set of snapshots of the register templates by storing incremental changes between a subset of the set of snapshots.

12. The processor of claim 8 , wherein the scheduler is further configured to restore a valid state for the processor by loading a valid register view data structure.

13. The processor of claim 12 , wherein the valid register view data structure is reconstructed from a valid register view snapshot.

14. The processor of claim 8 , wherein each register template stores inheritance vectors that define dependency and inheritance information referred to by a corresponding instructions block.

15. A computer system configured to implement a method of managing a reduced size register view data structure, the computer system comprising:

a memory to store a set of instructions; and

a processor coupled to the memory, the processor including a set of execution units, a global front end to receive an incoming instruction sequence and to group instructions from the incoming instruction sequence to form instruction blocks, and a scheduler to schedule execution of the instruction blocks to the set of execution units, the scheduler including a register view data structure, the scheduler to populate a register view data structure, wherein the register view data structure stores register information references by the instruction blocks as a set of register templates, to generate a set of snapshots of the register templates to reduce a size of the register view data structure, and to track a state of the processor to handle a branch miss-prediction using the register view data structure in accordance with execution of the instruction blocks.

16. The computer system of claim 15 , wherein the register view data structure, a source view data structure and an instruction view data structure are parts of a scheduler architecture of the processor.

17. The computer system of claim 15 , wherein the scheduler is further configured to determine a last valid register template snapshot in response to branch misprediction.

18. The computer system of claim 15 , wherein the scheduler is further configured to compress the set of snapshots of the register templates by storing incremental changes between a subset of the set of snapshots.

19. The computer system of claim 15 , wherein the scheduler is further configured to restore a valid state for the processor by loading a valid register view data structure.

20. The computer system of claim 19 , wherein the valid register view data structure is reconstructed from a valid register view snapshot.