High-speed current comparator suitable for nano-power circuit design
Systems and methods according to one or more embodiments are provided for a current comparator with biasing circuitry to provide for low power consumption and high-speed performance. In one example, a system includes an input port to receive a current pulse and an amplifier configured to provide a voltage pulse at an output port in response to the current pulse. The system also includes a first biasing circuit coupled between the output port and the input port to selectively limit a voltage at the input port. The system further includes a second biasing circuit coupled to the amplifier to selectively adjust a bias of the amplifier.
1. A system comprising:
an input port arranged to receive a current pulse;
an amplifier configured to provide a voltage pulse at an output port in response to the current pulse;
a first biasing circuit comprising a non-linear feedback circuit coupled between the output port and the input port and configured to selectively limit a voltage at the input port; and
a second biasing circuit coupled to the amplifier and configured to selectively adjust a bias of the amplifier.
2. The system of claim 1 , wherein the amplifier is configured as a class AB amplifier comprising a CMOS output stage.
3. The system of claim 1 , wherein the second biasing circuit is configured as a class AB amplifier biasing circuit.
4. The system of claim 3 , wherein the second biasing circuit comprises a positive bias voltage circuit and a negative bias voltage circuit.
5. The system of claim 4 , wherein the positive bias voltage circuit provides a selectively adjustable positive bias voltage to the amplifier.
6. The system of claim 4 , wherein the negative bias voltage circuit provides a selectively adjustable negative bias voltage to the amplifier.
7. The system of claim 4 , further comprising a bias current circuit, wherein the bias current circuit provides a selectively adjustable bias current to the amplifier to control a quiescent current of the amplifier.
8. The system of claim 1 , further comprising a selectively adjustable positive power source coupled to the first biasing circuit.
9. The system of claim 1 , further comprising a selectively adjustable negative power source coupled to the first biasing circuit.
10. A method comprising:
receiving, at an input port, a current pulse;
providing, by an amplifier, a voltage pulse at an output port in response to the current pulse;
selectively limiting, by a first biasing circuit comprising a non-linear feedback circuit coupled between the output port and the input port, a voltage at the input port; and
selectively adjusting, by a second biasing circuit coupled to the amplifier, a bias of the amplifier.
11. The method of claim 10 , wherein the amplifier is configured as a class AB amplifier comprising a CMOS output stage.
12. The method of claim 10 , wherein the second biasing circuit is configured as a class AB amplifier biasing circuit.
13. The method of claim 12 , wherein the second biasing circuit comprises a positive bias voltage circuit and a negative bias voltage circuit.
14. The method of claim 13 , further comprising selectively adjusting, by the positive bias voltage circuit, a positive bias voltage provided to the amplifier.
15. The method of claim 13 , further comprising selectively adjusting, by the negative bias voltage circuit, a negative bias voltage provided to the amplifier.
16. The method of claim 13 , further comprising selectively adjusting, by a bias current circuit, a bias current provided to the amplifier to control a quiescent current of the amplifier.
17. The method of claim 10 , further comprising selectively adjusting a positive power source coupled to the first biasing circuit.
18. The method of claim 10 , further comprising selectively adjusting a negative power source coupled to the first biasing circuit.