IP Library Granted Patent US 11,989,609
Granted Patent B2
US 11,989,609 · App. 15/808,362 · Granted May 21, 2024

Method of securing a comparison of data during the execution of a program

Inventors: Vincent Dupaquis (Biver, FR); Eric Le Cocquen (Saint Maximin la Sainte Beaume, FR)
Assignee: Rambus Inc.
G06K19/07372G06F7/02G06F11/14G06F21/52G06F21/60G06F21/75G09C1/00H04L9/004H04L63/0428G06F9/30021G06F2207/7271
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Quick Facts
Patent No.
US 11,989,609
App. No.
15/808,362
Granted
May 21, 2024
Kind
B2
Abstract

This disclosure relates to a method for securing the execution of a program by a processor, including a comparison instruction for comparing two data items, followed by a program operation which is selected as a function of a comparison result provided by the comparison instruction. The method may include, before the execution of the comparison instruction, calculating in various ways comparison data representative of the equality of the data to be compared, after the execution of the comparison instruction, verifying whether the comparison data calculated are consistent with the fact that the program operation is selected or not selected, and activating an error signal if the comparison data are mutually inconsistent or inconsistent with the result of the comparison.

Claims (58)

1. A method for securing an execution of a program by a first processing device, the method comprising:

subsequent to an execution of a first instruction of the program by the first processing device and prior to an execution of a data comparison function by the first processing device, receiving, from the first processing device and by a second processing device, an identifier of two data items on which the data comparison function is to be performed by the first processing device;

performing, by the second processing device, a first operation of a plurality of security operations to secure at least the data comparison function of the program, wherein the first operation computes, from the two data items, first comparison results comprising comparison variables representative of comparisons of the two data items;

subsequent to the execution of the data comparison function by the first processing device, receiving, from the first processing device and by the second processing device, an indication that the first processing device has executed a program branch of the program that corresponds to a second comparison result of the data comparison function, wherein the second comparison result identifies the two data items as equal;

responsive to receiving the indication that the first processing device has executed the program branch of the program, performing, by the second processing device, a second operation of the plurality of security operations to update a status indicator to indicate that the second comparison result identifies the two data items as equal;

performing, by the second processing device, a third operation of the plurality of security operations to verify whether the status indicator is consistent with the first comparison results; and

responsive to verifying that the status indicator is inconsistent with the first comparison results, performing, by the second processing device, a fourth operation of the plurality of security operations to enable an error signal to secure at least the data comparison function of the program executed by the first processing device, wherein securing the data comparison function secures the execution of the program by the first processing device.

2. The method of claim 1 , wherein the comparison variables includes at least two of:

a first binary comparison variable whose value is a function of equivalence of the two data items to be compared,

a second binary comparison variable equal to a combination of bits of a first binary word by a logic OR operation, the first binary word resulting from a bit-wise combination of the two data items to be compared by a logical exclusive-OR operation,

a third binary comparison variable equal to a combination of bits of a second binary word by a logic AND operation, the second binary word resulting from a bit-wise combination by the logic OR operation of one of the two data items to be compared with a binary one's complement of an other one of the two data items to be compared, or

a fourth binary comparison variable equal to a combination of bits of a third binary word by the logic OR operation, the third binary word resulting from a bit-wise combination by the logic AND operation of one of the two data items to be compared with the binary one's complement of the other one of the two data items to be compared.

3. The method of claim 2 , wherein at least one of the two data items to be compared is read from a memory at each calculation of one of the comparison variables.

4. The method of claim 1 , wherein updating the status indicator to indicate that the second comparison result identifies the two data items as equal comprises activating a flag to indicate that the two data items are equal.

5. The method of claim 1 , wherein the two data items to be compared are respectively a first block and a second block, the execution of the data comparison function comprising individually comparing each word of the first block with a corresponding word of the second block,

wherein performing the first operation of the plurality of security operations comprises counting a number of equal words between the first and second blocks, wherein the data comparison function compares the number of equal words between the first and second blocks with a number of words in each of the first and second blocks.

6. The method of claim 5 , wherein performing the first operation of the plurality of security operations further comprises:

counting a number of different words between the first and second blocks;

counting a number of equal words between the first and second blocks; and

determining whether a sum of the number of equal words and the number of different words between the first and second blocks is equal to the number of words in each of the first and second blocks.

7. The method of claim 1 , wherein the two data items to be compared are respectively a first block and a second block, wherein performing the first operation of the plurality of security operations, comprises:

calculating a first sum of words of the first block and a second sum of words of the second block.

8. The method of claim 7 , wherein calculating the first sum comprises adding successive values of a word counter counting words of the first block,

wherein performing the first operation of the plurality of security operations, comprises:

calculating a counter sum of the successive values of the word counter from a number of words in each of the first and second blocks; and

modifying the first sum by subtracting the counter sum from the first sum.

9. A circuit for securing an execution of a program by a first processing device, the circuit comprising:

a second processing device configured to:

subsequent to an execution of a first instruction of the program by the first processing device and prior to an execution of a data comparison function by the first processing device, receive, from the first processing device and by the second processing device, an identifier of two data items on which the data comparison function is to be performed by the first processing device;

perform, by the second processing device, a first operation of a plurality of security operations to secure at least the data comparison function of the program, wherein the first operation computes, from the two data items, first comparison results comprising comparison variables representative of comparisons of the two data items;

subsequent to the execution of the data comparison function by the first processing device, receive, from the first processing device and by the second processing device, an indication that the first processing device has executed a program branch of the program that corresponds to a second comparison result of the data comparison function, wherein the second comparison result identifies the two data items as equal;

responsive to receiving the indication that the first processing device has executed the program branch of the program, perform, by the second processing device, a second operation of the plurality of security operations to update a status indicator to indicate that the second comparison result identifies the two data items as equal;

perform, by the second processing device, a third operation of the plurality of security operations to verify whether the status indicator is consistent with the first comparison results; and

responsive to verifying that the status indicator is inconsistent with the first comparison results, perform, by the second processing device, a fourth operation of the plurality of security operations to enable an error signal to secure at least the data comparison function of the program executed by the first processing device, wherein securing the data comparison function secures the execution of the program by the first processing device.

10. The circuit of claim 9 , wherein the comparison variables includes at least two of:

a first binary comparison variable whose value is a function of equivalence of the two data items to be compared,

a second binary comparison variable equal to a combination of bits of a first binary word by a logic OR operation, the first binary word resulting from a bit-wise combination of the two data items to be compared by a logical exclusive-OR operation,

a third binary comparison variable equal to a combination of bits of a second binary word by a logic AND operation, the second binary word resulting from a bit-wise combination by the logic OR operation of one of the two data items to be compared with a binary one's complement of an other one of the two data items to be compared, or

a fourth binary comparison variable equal to a combination of bits of a third binary word by the logic OR operation, the third binary word resulting from a bit-wise combination by the logic AND operation of one of the two data items to be compared with the binary one's complement of the other one of the two data items to be compared.

11. The circuit of claim 10 , wherein at least one of the two data items to be compared is read from a memory at each calculation of one of the comparison variables.

12. The circuit of claim 9 , wherein to update the status indicator to indicate that the second comparison result identifies the two data items as equal, the second processing device further configured to activate a flag to indicate that the two data items are equal.

13. The circuit of claim 9 , wherein the two data items to be compared are respectively a first block and a second block, wherein the execution of the data comparison function individually compares each word of the first block with a corresponding word of the second block, wherein to perform the first operation of the plurality of security operations, the second processing device configured to:

count a number of equal words between the first and second blocks, wherein the data comparison function compares the number of equal words between the first and second blocks with a number of words in each of the first and second blocks.

14. The circuit of claim 13 , wherein to perform the first operation of the plurality of security operations, the second processing device configured to:

count a number of different words between the first and second blocks;

count a number of equal words between the first and second blocks; and

determine whether a sum of the number of equal words and the number of different words between the first and second blocks is equal to the number of words in each of the first and second blocks.

15. The circuit of claim 9 , wherein the two data items to be compared are respectively a first block and a second block, wherein to perform the first operation of the plurality of security operations, the second processing device configured to: calculate a first sum of words of the first block and a second sum of words of the second block.

16. The circuit of claim 15 , wherein the first sum includes successive values of a word counter counting words of the first block, wherein to perform the first operation of the plurality of security operations, the second processing device configured to:

calculate a counter sum of the successive values of the word counter from a number of words in each of the first and second blocks; and

modify the first sum by subtracting the counter sum from the first sum.

17. A non-transitory computer readable medium comprising instructions for securing an execution of a program by a first processing device and that, responsive to execution by a computer, perform operations comprising:

subsequent to an execution of a first instruction of the program by the first processing device and prior to an execution of a data comparison function by the first processing device, receiving, from the first processing device and by a second processing device, an identifier of two data items on which the data comparison function is to be performed by the first processing device;

performing, by the second processing device, a first operation of a plurality of security operations to secure at least the data comparison function of the program, wherein the first operation computes, from the two data items, first comparison results comprising comparison variables representative of comparisons of the two data items;

subsequent to the execution of the data comparison function by the first processing device, receiving, from the first processing device and by the second processing device, an indication that the first processing device has executed a program branch of the program that corresponds to a second comparison result of the data comparison, wherein the second comparison result identifies the two data items as equal;

responsive to receiving the indication that the first processing device has executed the program branch of the program, performing, by the second processing device, a second operation of the plurality of security operations to update a status indicator to indicate that the second comparison result identifies the two data items as equal;

performing, by the second processing device, a third operation of the plurality of security operations to verify whether the status indicator is consistent with the first comparison results; and

responsive to verifying that the status indicator is inconsistent with the first comparison results, performing, by the second processing device, a fourth operation of the plurality of security operations to enable an error to secure at least the data comparison function of the program executed by the first processing device, wherein securing the data comparison function secures the execution of the program by the first processing device.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2019
From: VERIMATRIX
To: RAMBUS INC.
Reel/Frame 051262/0413 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Nov 21, 2019
From: GLAS SAS, AS AGENT
To: INSIDE SECURE
Reel/Frame 051076/0306 →
CHANGE OF ADDRESS Recorded Oct 16, 2019
From: VERIMATRIX
To: VERIMATRIX
Reel/Frame 050733/0003 →
CHANGE OF NAME Recorded Oct 7, 2019
From: INSIDE SECURE
To: VERIMATRIX
Reel/Frame 050647/0428 →
SECURITY INTEREST Recorded Feb 27, 2019
From: INSIDE SECURE
To: GLAS SAS, AS SECURITY AGENT
Reel/Frame 048449/0887 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2018
From: DUPAQUIS, VINCENT; LE COCQUEN, ERIC
To: INSIDE SECURE
Reel/Frame 044910/0232 →
Priority Claims (1)
FR 1554348 · May 13, 2015 · national
Continuity (2)
Continuation PCTFR2016051090 · May 10, 2016
Related Publication 20180144228A1 · May 24, 2018