IP Library Granted Patent US 10,264,234
Granted Patent B2
US 10,264,234 · App. 15/811,033 · Granted Apr 16, 2019

Multi-processor support for array imagers

Inventors: John T. Bretscher (Elgin, IL); Randall S. Vaas (Wyoming, MI)
Assignee: Google Technology Holdings LLC
H04N13/161H04N5/2258H04N5/23229H04N13/282H04N19/107H04N19/436H04N19/439H04N19/503H04N19/593H04N19/597H04N19/62
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Quick Facts
Patent No.
US 10,264,234
App. No.
15/811,033
Granted
Apr 16, 2019
Kind
B2
Abstract

Using the techniques discussed herein, a set of images is captured by one or more array imagers ( 106 ). Each array imager includes multiple imagers configured in various manners. Each array imager captures multiple images of substantially a same scene at substantially a same time. The images captured by each array image are encoded by multiple processors ( 112, 114 ). Each processor can encode sets of images captured by a different array imager, or each processor can encode different sets of images captured by the same array imager. The encoding of the images is performed using various image-compression techniques so that the information that results from the encoding is smaller, in terms of storage size, than the uncompressed images.

Claims (46)

1. An electronic device that captures and encodes imagery, the electronic device comprising:

one or more array imagers, each of the one or more array imagers comprising a plurality of imagers, the one or more array imagers operable to capture a plurality of sets of images, each set of images comprising a plurality of images that depict respective portions of a scene;

at least one non-transitory computer-readable media that stores instructions; and

two or more processors that execute the instructions to:

obtain the plurality of sets of images captured by the one or more array imagers of the electronic device; and

respectively encode the plurality of sets of images, wherein each set of images is encoded by a single respective one of the two or more processors.

2. The electronic device of claim 1 , wherein the one or more array imagers comprise a single array imager.

3. The electronic device of claim 2 , wherein the two or more processors respectively encode the plurality of sets of images captured by the single array imager in an alternating fashion.

4. The electronic device of claim 1 , wherein:

the one or more array imagers comprise:

a first array imager operable to capture a first group of the sets of images; and

a second array imager operable to capture a second group of the sets of images; and

the two or more processors comprise:

a first processor operatively connected to the first array imager and operable to encode each set of images included in the first group; and

a second processor operatively connected to the second array imager and operable to encode each set of images included in the second group.

5. The electronic device of claim 1 , wherein:

the two or more processors perform at least one of spatial prediction and spectral prediction to respectively encode each set of images at a first encoding stage;

the electronic device further includes one or more additional processors that perform at least one of temporal prediction and three-dimensional encoding to respectively further encode each set of images at a second encoding stage that occurs subsequent to the first encoding stage; and

the one or more additional processors are distinct from the two or more processors such that the electronic device comprises at least three processors.

6. The electronic device of claim 1 , wherein to respectively encode the plurality of sets of images, the two or more processors:

perform at least one of spatial prediction and spectral prediction to respectively encode each set of images at a first encoding stage; and

perform at least one of temporal prediction and three-dimensional encoding to respectively further encode each set of images at a second encoding stage that occurs subsequent to the first encoding stage;

wherein the two or more processors that perform the first encoding stage are the same processors that perform the second encoding stage.

7. The electronic device of claim 1 , wherein at least two of the plurality of imagers of the one or more array imagers have at least one characteristic that is different from each other, the at least one different characteristic comprising at least one of: a spectral sensitivity, a filter, or a resolution.

8. The electronic device of claim 1 , wherein at least a first imager of the plurality of imagers of the one or more array imagers senses humanly-visible light, and wherein at least a second imager of the plurality of imagers of the one or more array imagers senses non-humanly-visible light.

9. The electronic device of claim 1 , further comprising:

a compression engine implemented by at least one of the two or more processors to:

determine a respective amount of compression that each of a plurality of different encoding techniques will provide, the plurality of different encoding techniques comprising one or more of spectral prediction, spatial prediction, and temporal prediction; and

select the encoding technique that provides the largest amount of compression for performance by the two or more processors to respectively encode the plurality of sets of images.

10. The electronic device of claim 1 , wherein, for each set of images, each of the plurality of images is captured within one second of respective times at which the other images within such set of images are captured.

11. A method for image capture and multi-processor encoding, the method comprising:

capturing, by one or more array imagers of an electronic device, a first set of images, the first set of images comprising a first plurality of images that depict respective portions of a first scene at a same first time;

capturing, by the one or more array imagers of the electronic device, a second set of images, the second set of images comprising a second plurality of images that depict respective portions of a second scene at a same second time;

encoding, by a first processor of the electronic device, each of the first plurality of images included within the first set of images, each of the first plurality of images encoded by the same first processor; and

encoding, by a second processor of the electronic device that is distinct from the first processor, each of the second plurality of images included within the second set of images, each of the second plurality of images encoded by the same second processor.

12. The method of claim 11 , wherein:

capturing, by the one or more array imagers of an electronic device, the first set of images comprises capturing, by a first array imager of the electronic device, the first set of images; and

capturing, by the one or more array imagers of an electronic device, the second set of images comprises capturing, by the same first array imager of the electronic device, the second set of images.

13. The method of claim 12 , wherein:

capturing, by the first array imager, the first set of images and the second set of images comprises capturing, by the first array imager, a plurality of sets of images; and

encoding, by the first processor, each of the first plurality of images and encoding, by the second processor, each of the second plurality of images comprises:

encoding, by the first processor, a first group of the plurality of sets of images; and

encoding, by the second processor that is distinct from the first processor, a second group of the plurality of sets of images, wherein the first group and the second group respectively include alternating sets of images.

14. The method of claim 11 , wherein:

capturing, by the one or more array imagers of an electronic device, the first set of images comprises capturing, by a first array imager of the electronic device, the first set of images; and

capturing, by the one or more array imagers of an electronic device, the second set of images comprises capturing, by a second array imager of the electronic device that is distinct from the first array imager, the second set of images.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 13, 2017
From: BRETSCHER, JOHN T.; VAAS, RANDALL S.
To: MOTOROLA MOBILITY LLC
Reel/Frame 044110/0994 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 13, 2017
From: MOTOROLA MOBILITY LLC
To: GOOGLE TECHNOLOGY HOLDINGS LLC
Reel/Frame 044111/0242 →
Continuity (4)
Continuation 15091733 · Apr 6, 2016
Continuation 14319285 · Jun 30, 2014
Provisional Application 61932852 · Jan 29, 2014
Related Publication 20180070072A1 · Mar 8, 2018