Data communication system and semiconductor device

1. A data communication system comprising:

a clock signal line for transmitting a clock signal;

a data signal line for transmitting data;

a first data communication circuit for outputting a clock signal to the clock signal line, and receiving input of data from the data signal line, or outputting data as open drain output or open collector output to the data signal line;

a second data communication circuit for receiving input of a clock signal from the clock signal line, and receiving input of data from the data signal line, or outputting data as open drain output or open collector output to the data signal line;

a first pull-up resistor connected between the data signal line and a wiring of a power supply potential on a higher potential side;

a second pull-up resistor for selectively pulling up the data signal line, wherein one end of the second pull-up resistor is connected to the data signal line; and

a pull-up control circuit that is connected to the second pull-up resistor, wherein when a power supply potential on the higher potential side is supplied, the pull-up control circuit outputs a pull-up control signal at a high level to the other end of the second pull-up resistor at least in response to a clock signal.

2. The data communication system according to claim 1 ,

wherein the pull-up control circuit includes a switch circuit that is connected between a wiring of the power supply potential on the higher potential side and the other end of the second pull-up resistor, and is turned on at least in response to a clock signal.

3. The data communication system according to claim 2 ,

wherein the switch circuit includes a P-channel transistor having a source connected to the wiring of the power supply potential on the higher potential side and a drain connected to the other end of the second pull-up resistor.

4. The data communication system according to claim 1 ,

wherein the pull-up control circuit outputs a pull-up control signal at a high level when a clock signal is at a low level.

5. The data communication system according to claim 1 ,

wherein when a first predetermined period has elapsed after a clock signal changed to a low level, the pull-up control circuit starts outputting a pull-up control signal at a high level, and when a second predetermined period has elapsed after the clock signal changed to a low level, stops outputting the pull-up control signal at a high level.

6. The data communication system according to claim 1 ,

wherein the pull-up control circuit outputs a pull-up control signal at a high level when the first data communication circuit sets an idle state.

7. The data communication system according to claim 1 ,

wherein the first data communication circuit activates an idle state signal before setting the idle state after data communication ends, and the pull-up control circuit outputs a pull-up control signal at a high level in response to the idle state signal.

8. The data communication system according to claim 1 ,

wherein the first data communication circuit outputs a clock signal to the clock signal line by push-pull driving.

9. The data communication system according to claim 1 ,

wherein the first and second data communication circuits perform communication in accordance with an I2C (I squared C) bus communication protocol.

10. The data communication system according to claim 1 , further comprising:

one first data communication circuit and a plurality of second data communication circuits.

11. A semiconductor device that is used in a data communication system including a clock signal line for transmitting a clock signal and a data signal line for transmitting data, comprising:

a clock signal input/output circuit for receiving input of a clock signal from the clock signal line, or outputting a clock signal to the clock signal line;

a data input/output circuit for receiving input of data from the data signal line, or outputting data as open drain output or open collector output to the data signal line; and

a pull-up control circuit that outputs a pull-up control signal at a high level from an output terminal at least in response to a clock signal in order to pull up the data signal line when a power supply potential on a higher potential side is supplied.

12. The semiconductor device according to claim 11 ,

wherein the pull-up control circuit includes a switch circuit that is connected between an interconnect of the power supply potential on the higher potential side and the output terminal, and is turned on at least in response to a clock signal.

13. The semiconductor device according to claim 11 ,

wherein the pull-up control circuit outputs a pull-up control signal at a high level when a clock signal is at a low level.

14. The semiconductor device according to claim 11 ,

wherein the pull-up control circuit starts outputting a pull-up control signal at a high level when a first predetermined period has elapsed after a clock signal changed to a low level, and stops outputting the pull-up control signal at a high level when a second predetermined period has elapsed after the clock signal changed to a low level.

15. The semiconductor device according to claim 11 , further comprising:

a communication control circuit that controls communication operations of the clock signal output circuit and the data input/output circuit,

wherein the pull-up control circuit outputs a pull-up control signal at a high level when the communication control circuit sets an idle state.