Bridged integrated circuits

1. A system comprising:

a first integrated circuit chip comprising application logic for one or more executable applications; and

a second integrated circuit chip communicatively coupled to the first integrated circuit chip, the second integrated circuit chip comprising:

an instruction decoder configured to decode instructions for executing the one or more executable applications; and

a communication interface configured to transmit the decoded instructions to the first integrated circuit chip to execute the one or more executable applications on the first integrated circuit chip,

wherein the decoded instructions are executed in a deterministic manner such that each decoded instruction is executed at a respective predetermined timing.

2. The system of claim 1 , wherein operations of the first integrated circuit chip and the second integrated circuit chip are synchronous.

3. The system of claim 1 , further comprising a data store configured to store the instructions for executing the one or more executable applications on the first integrated circuit chip, and

wherein the instruction decoder is configured to obtain the instructions from the data store.

4. The system of claim 3 , wherein the data store is integrated in the second integrated circuit chip.

5. The system of claim 3 , wherein the data store is separate from the second integrated circuit chip.

6. The system of claim 1 , wherein the first integrated circuit chip is an ASIC (Application-Specific Integrated Circuit), and wherein the second integrated circuit chip is a FPGA (Field-Programmable Gate Array).

7. The system of claim 6 , further comprising:

a circuit board comprising an ASIC socket,

wherein the FPGA is permanently bonded to the circuit board, and

wherein the ASIC is plugged in the ASIC socket.

8. The system of claim 6 ,

wherein the system further comprises multiple sets of SerDes (Serializer/Deserializer), and

wherein the ASIC and the FPGA are communicatively coupled using the multiple sets of SerDes.

9. The system of claim 8 ,

wherein the system further comprises a GPIO (general purpose input/output), and

wherein the ASIC and the FPGA are communicatively coupled using the GPIO to provide an interface for debugging errors in a boot sequence.

10. The system of claim 8 ,

wherein the FPGA further comprises:

a processor;

external I/O interface configured to obtain input data from an external component; and

a buffer configured to store a portion of the input data,

wherein the communication interface of the FPGA is further configured to transmit the input data to the ASIC via the multiple sets of SerDes, and

wherein the ASIC further comprises:

a memory store configured to store (i) the decoded instructions from the FPGA, and (ii) the input data from the FPGA.

11. The system of claim 10 ,

wherein the one or more executable applications include a machine learning model,

wherein the decoded instructions from the FPGA instructs the ASIC to generate, based on the input data and using the machine learning model, output data indicating a type of objects, among multiple types of candidate objects, that is included in the input data, and

wherein the ASIC is configured to transmit the output data to the FPGA via the multiple sets of SerDes.

12. The system of claim 11 , wherein the FPGA is configured to transmit the output data to the external component via the external I/O interface.

13. The system of claim 11 ,

wherein the one or more executable applications include a second machine learning model,

wherein the FPGA is configured to:

determine, based on the output data, that a particular portion of the input data requires additional processing; and

in response to determining that the particular portion of the input data requires additional processing, transmit decoded instructions to instruct the ASIC to generate, based on the particular portion of the input data and using the second machine learning model, second output data.

14. The system of claim 10 ,

wherein the one or more executable applications include a video decoder,

wherein the input data includes an encoded signal, and

wherein the decoded instructions from the FPGA instructs the ASIC to generate, based on the input data and using the video decoder, output data representing a decoded signal, and

wherein the ASIC is configured to transmit the output data to the FPGA via the multiple sets of SerDes.

15. A computer-implemented method, comprising:

obtaining, by a FPGA, instructions for executing one or more executable applications stored in an ASIC;

decoding, by the FPGA, the instructions for executing the one or more executable applications;

transmitting, from the FPGA to the ASIC, the decoded instructions and input data for the one or more executable applications;

executing, by the ASIC and based on the decoded instructions and the input data, the decoded instructions to execute the one or more executable applications to generate output data; and

transmitting, from the ASIC to the FPGA, the output data,

wherein the decoded instructions are executed in a deterministic manner such that each decoded instruction is executed at a respective predetermined timing.

16. The method of claim 15 , wherein operations of the FPGA and the ASIC are synchronous.

17. The method of claim 15 , wherein transmitting, from the FPGA and to the ASIC, the input data further comprises:

encrypting, by the FPGA, a first portion of the input data using a first key value;

updating, by the FPGA, the first key value to generate a second key value;

decrypting, by the ASIC, the first portion of the encrypted input data using the first key value without receiving the first key value from the FPGA;

updating, by the ASIC, the first key value to generate the second key value;

encrypting, by the FPGA, a second portion of the input data using the second key value; and

decrypting, by the ASIC, the second portion of the encrypted input data using the second key value.

18. A method for executing an executable application on an ASIC, the method comprising:

receiving, from a FPGA and by an ASIC, data representing (i) decoded instructions, (ii) input data for executing one or more executable applications that are stored in the ASIC, and (iii) memory locations for storing the decoded instructions and the input data;

storing, by the ASIC, the decoded instructions and the input data at the memory locations;

obtaining, by the ASIC, the decoded instructions and the input data from the memory locations;

executing, by the ASIC and based on (i) the decoded instructions, (ii) the input data, and (iii) application logic for the one or more executable applications to generate output data; and

transmitting, from the ASIC to the FPGA, the output data.

19. The method of claim 18 , wherein operations of the FPGA and the ASIC are synchronous.