Virtual processor enabling real-time in situ disassembly and debugging in SoC environment
The example embodiments are directed to a system and method for a virtual processor that enables real-time in situ disassembly and debugging. In one example, the method includes implementing a virtual processor in field programmable gate array (FPGA) programmable logic, the virtual processor comprising a virtual version of a target system, capturing data representative of operations in the virtual processor using a bus access device configured to provide direct access to components of the virtual processor, streaming the data to the embedded processor, storing the data in the memory device, and performing in-situ disassembly and debugging.
1. A computing system comprising:
a virtual processor implemented in field programmable gate array (FPGA) programmable logic, the virtual processor comprising a virtual version of a target system;
a memory device storing instructions; and
an embedded processor coupled to the FPGA programmable logic via a virtual processor interface, the embedded processor being distinct from the FPGA programmable logic and configured to execute the instructions, wherein the executed instructions cause the embedded processor to:
capture data representative of operations in the virtual processor using a bus access device configured to provide direct access to components of the virtual processor;
stream the data to the embedded processor via the virtual processor interface;
store the data in the memory device; and
perform, substantially in real time while the target system is running, in-situ disassembly and debugging of the data representative of the operations of the virtual processor, wherein the debugging comprises one or more of a tracing operation, a breakpoint operation, a watchpoint operation, a triggering operation, a halting operation, or an event counting operation.
2. The computing system of claim 1 , wherein the memory device is a random-access memory (RAM)-based first-in-first-out (FIFO) memory.
3. The computing system of claim 1 , wherein the data is streamed to the embedded processor using a using a direct memory access (DMA) channel.
4. The computing system of claim 1 , wherein the virtual processor implemented in FPGA logic is instead implemented in Application Specific Integrated Circuit (ASIC) logic.
5. The computing system of claim 1 , wherein the memory device is double data rate (DDR) memory and the data stored in the memory device is written into the memory device via a DMA transfer.
6. The computing system of claim 1 , wherein the hardware and operations of the target system are emulated in software.
7. The computing system of claim 1 , wherein the data is sampled at a sampling rate of a central processing unit (CPU) corresponding to the virtual processor.
8. The computing system of claim 1 , wherein the embedded processor further comprises one or more processing cores on a system-on-chip (SoC).
9. A computer-implemented method comprising:
implementing a virtual processor in field programmable gate array (FPGA) programmable logic, the virtual processor comprising a virtual version of a target system;
capturing data representative of operations in the virtual processor using a bus access device configured to provide direct access to components of the virtual processor;
streaming the data to an embedded processor via a virtual processor interface, the embedded processor coupled to the FPGA programmable logic via the virtual processor interface, the embedded processor being distinct from the FPGA programmable logic;
storing the data in the memory device; and
performing, substantially in real time while the target system is running, in-situ disassembly and debugging of the data representative of the operations of the virtual processor, wherein the debugging comprises one or more of a tracing operation, a breakpoint operation, a watchpoint operation, a triggering operation, a halting operation, or an event counting operation.
10. The computer-implemented method of claim 9 , wherein the memory device is a random-access memory (RAM)-based first-in-first-out (FIFO) memory.
11. The computer-implemented method of claim 9 , wherein the data is streamed to the embedded processor using a using a direct memory access (DMA) channel.
12. The computer-implemented method of claim 9 , wherein the virtual processor implemented in FPGA logic is instead implemented in Application Specific Integrated Circuit (ASIC) logic.
13. The computer-implemented method of claim 9 , wherein the memory device is double data rate (DDR) memory and the data stored in the memory device is written into the memory device via a DMA transfer.
14. The computer-implemented method of claim 9 , wherein the hardware and operations of the target system are emulated in software.
15. The computer-implemented method of claim 9 , wherein the data is sampled at a sampling rate of a central processing unit (CPU) corresponding to the virtual processor.
16. The computer-implemented method of claim 9 , wherein the embedded processor further comprises one or more processing cores on a system-on-chip (SoC).
17. A non-transitory computer readable medium having stored therein instructions that when executed cause a computer to perform a method comprising:
implementing a virtual processor in field programmable gate array (FPGA) programmable logic, the virtual processor comprising a virtual version of a target system;
capturing data representative of operations in the virtual processor using a bus access device configured to provide direct access to components of the virtual processor;
streaming the data to the embedded processor;
storing the data in the memory device; and
performing, substantially in real time while the target system is running, in-situ disassembly and debugging of the data representative of the operations of the virtual processor, wherein the debugging comprises one or more of a tracing operation, a breakpoint operation, a watchpoint operation, a triggering operation, a halting operation, or an event counting operation.