IP Library Granted Patent US 10,763,371
Granted Patent B2
US 10,763,371 · App. 15/813,735 · Granted Sep 1, 2020

Thin-film transistor, method of manufacturing the same, and display device

Inventors: Narihiro Morosawa (Kanagawa, JP); Yoshihiro Oshima (Kanagawa, JP)
Assignee: Joled Inc.
H01L29/7869H01L29/41733H01L29/66969H01L29/78618
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Quick Facts
Patent No.
US 10,763,371
App. No.
15/813,735
Granted
Sep 1, 2020
Kind
B2
Abstract

A thin film transistor is provided. The thin film transistor includes an oxide semiconductor layer including a source region, a drain region, and a channel region wherein a portion of the source and drain regions has an oxygen concentration less than the channel region. Further provided is a thin film transistor that includes an oxide semiconductor layer including a source region, a drain region, and a channel region, wherein a portion of the source and drain regions includes a dopant selected from the group consisting of aluminum, boron, gallium, indium, titanium, silicon, germanium, tin, lead, and combinations thereof.

Claims (23)

1. A thin film transistor comprising:

a gate electrode,

a gate insulating film,

an oxide semiconductor layer having an island-like shape including

a source region,

a drain region, and

a channel region, and

a high-resistance material layer that is provided on and directly contacts the source and drain regions,

wherein the gate electrode is provided between the gate insulating film and the high-resistance material layer and the gate electrode directly contacts with the gate insulating film and the high-resistance material layer,

wherein a portion of the source and drain regions includes a dopant selected from the group consisting of aluminum, boron, gallium, indium, titanium, silicon, germanium, tin, lead, and combinations thereof,

wherein a density of the dopant in the source and drain regions of the oxide semiconductor layer having the island-like shape is higher than the channel region of the oxide semiconductor layer having the island-like shape, and

wherein the thin film transistor is a top gate transistor.

2. The thin film transistor of claim 1 , wherein the portion of the source and drain regions is a low-resistance region extending in a depth direction from an upper face thereof.

3. The thin film transistor of claim 2 , wherein the low-resistance region extends at least within 30 nm in the depth direction from the upper face thereof.

4. The thin film transistor of claim 1 , wherein the high-resistance material layer includes a constituent selected from the group consisting of titanium, aluminum, and indium, boron, gallium, silicon, germanium, tin, and lead.

5. The thin film transistor of claim 1 , wherein the high-resistance material layer includes any one of a plurality of island-shaped metal films and a plurality of island-shaped nonmetal films.

6. The thin film transistor of claim 5 , wherein any one of the island-shaped metal films and the island-shaped nonmetal films are spaced apart so as to provide a clearance gap.

7. The thin film transistor of claim 5 , wherein the portion of the source and drain regions is a low-resistance region extending in a depth direction from an upper face thereof, and wherein a first portion of any one of the island-shaped metal films and the island-shaped nonmetal films is in contact with the low resistance region and a second portion of any one of the island-shaped metal films and the island-shaped nonmetal films is in contact with a gate electrode.

8. The thin film transistor of claim 1 , further including an insulating layer.

9. The thin film transistor of claim 1 further including a source electrode and a drain electrode.

10. The thin film transistor of claim 1 , wherein the density of the dopant in the source and drain region is equal to or higher than 1×10 19 /cm 3 .

11. The thin film transistor of claim 1 , wherein the high-resistance material layer includes aluminum oxide, indium oxide or titanium oxide.

12. The thin film transistor of claim 1 , wherein the high-resistance material layer is provided on and directly contacts a low-resistance region of the oxide semiconductor layer.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 29, 2017
From: MOROSAWA, NARIHIRO; OSHIMA, YOSHIHIRO
To: SONY CORPORATION
Reel/Frame 044252/0084 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 29, 2017
From: SONY CORPORATION
To: JOLED INC.
Reel/Frame 044252/0110 →
Cited By (4)
US 12,199,186 US 12,261,119 US 12,363,955 US 12,414,334