Semiconductor device
Provided is a semiconductor device including a vertical Hall element with improved sensitivity. The vertical Hall element includes: a semiconductor layer of a second conductivity type formed on the semiconductor substrate; a plurality of electrodes aligned along a straight line on a surface of the semiconductor layer and being impurity regions of the second conductivity type being higher in concentration than the semiconductor layer; a plurality of electrode isolation diffusion layers of the first conductivity type respectively arranged between adjacent electrodes of the plurality of electrodes on the surface of the semiconductor layer to isolate the plurality of electrodes from one another; and embedded layers being an impurity region of the second conductivity type which is higher in concentration than the semiconductor layer and being respectively provided substantially right below one of the plurality of electrode isolation diffusion layers between the semiconductor substrate and the semiconductor layer.
1. A semiconductor device, comprising:
a semiconductor substrate of a first conductivity type; and
a vertical Hall element provided on the semiconductor substrate,
the vertical Hall element including:
a semiconductor layer of a second conductivity type formed on the semiconductor substrate;
a plurality of electrodes aligned along a straight line on a surface of the semiconductor layer, and formed from impurity regions of the second conductivity type having a concentration higher than that of the semiconductor layer,
a plurality of electrode isolation diffusion layers of the first conductivity type respectively arranged between adjacent electrodes of the plurality of electrodes on the surface of the semiconductor layer to isolate the plurality of electrodes from one another; and
embedded layers formed from an impurity region of the second conductivity type having a concentration higher than that of the semiconductor layer, and respectively provided substantially right below one of the plurality of electrode isolation diffusion layers between the semiconductor substrate and the semiconductor layer.
2. The semiconductor device according to claim 1 , wherein none of the embedded layers are provided right below the plurality of electrodes.
3. The semiconductor device according to claim 1 , wherein the semiconductor layer includes an epitaxial layer.
4. The semiconductor device according to claim 2 , wherein the semiconductor layer includes an epitaxial layer.
5. The semiconductor device according to claim 1 , wherein the surface of the semiconductor layer and surfaces of the plurality of electrode isolation diffusion layers are covered with an insulating film, except for regions in which the plurality of electrodes are formed.
6. The semiconductor device according to claim 2 , wherein the surface of the semiconductor layer and surfaces of the plurality of electrode isolation diffusion layers are covered with an insulating film, except for regions in which the plurality of electrodes are formed.
7. The semiconductor device according to claim 3 , wherein the surface of the semiconductor layer and surfaces of the plurality of electrode isolation diffusion layers are covered with an insulating film, except for regions in which the plurality of electrodes are formed.
8. The semiconductor device according to claim 1 , wherein a number of the plurality of electrodes is at least three.
9. The semiconductor device according to claim 2 , wherein a number of the plurality of electrodes is at least three.
10. The semiconductor device according to claim 3 , wherein a number of the plurality of electrodes is at least three.
11. The semiconductor device according to claim 4 , wherein a number of the plurality of electrodes is at least three.