DUAL-SUPPLY ANALOG CIRCUITRY FOR SENSING SURFACE EMG SIGNALS
Dual-supply analog circuitry for amplifying surface EMG (sEMG) signals is described. The circuitry includes a differential amplifier configured to be powered from dual-supply voltages. A positive input terminal of the differential amplifier is configured to be DC-coupled to a first sEMG electrode of a dry sEMG electrode pair and a negative input terminal of the differential amplifier is configured to be DC-coupled to a second sEMG electrode of the dry sEMG electrode pair.
1 . A surface electromyography (sEMG) system comprising:
a pair of dry sEMG electrodes; and
amplification circuitry comprising a first differential amplifier configured to be powered from dual-supply voltages,
wherein a first sEMG electrode of the pair of dry sEMG electrodes is DC-coupled to a positive input terminal of the first differential amplifier and a second sEMG electrode of the pair of dry sEMG electrodes is DC-coupled to a negative input terminal of the first differential amplifier.
2 . The sEMG system of claim 1 , wherein the first differential amplifier is configured to have a common-mode voltage of approximately 0 volts.
3 . The sEMG system of claim 1 , wherein the first differential amplifier is configured to have an input impedance of at least one Giga Ohm.
4 . The sEMG system of claim 3 , wherein the first differential amplifier is configured to have an input impedance of at least one Tera Ohm.
5 . The sEMG system of claim 1 , wherein the first differential amplifier is configured to have a gain of less than 50.
6 . The sEMG system of claim 5 , wherein the first differential amplifier is configured to have a gain of less than 15.
7 . The sEMG system of claim 1 , wherein the first differential amplifier comprises a field-effect transistor (FET).
8 . The sEMG system of claim 1 , further comprising:
a first resistor arranged between the first sEMG electrode and the positive input terminal of the first differential amplifier; and
a second resistor arranged between the second sEMG electrode and the negative input terminal of the first differential amplifier.
9 . The sEMG system of claim 1 , wherein the amplification circuitry further comprises:
a second differential amplifier having an input coupled to an output terminal of the first differential amplifier.
10 . The sEMG system of claim 9 , wherein the second differential amplifier is configured to be powered from a single supply voltage.
11 . The sEMG system of claim 9 , wherein the second differential amplifier is configured to be powered from dual-supply voltages.
12 . The sEMG system of claim 9 , wherein the second differential amplifier is AC-coupled to the output terminal of the first differential amplifier.
13 . The sEMG system of claim 9 , wherein a gain of the second differential amplifier is larger than a gain of the first differential amplifier.
14 . The sEMG system of claim 9 , wherein the amplification circuitry further comprises:
a third differential amplifier having an input coupled to an output of the second differential amplifier.
15 . The sEMG system of claim 1 , further comprising:
an analog-to-digital converter coupled to an output of the amplification circuitry; and
at least one processor coupled to the analog-to-digital converter, wherein the at least one processor is configured to perform digital signal processing on a signal received from the analog-to-digital converter.
16 . The sEMG system of claim 1 , wherein the pair of dry sEMG electrodes are arranged on a wearable device configured to be worn on or around a body part of the user.
17 . The sEMG system of claim 1 , further comprising:
at least one isolation component configured to provide galvanic isolation between components of the sEMG system having digital data communication; and
at least one isolated power supply configured to provide operating power to one or more of the components of the sEMG system isolated using the at least one isolation component.
18 . Amplification circuitry, comprising:
a first differential amplifier configured to be powered by dual-supply voltages, wherein the first differential amplifier is further configured to have a common-mode voltage of approximately 0 volts, wherein an input impedance of the first differential amplifier is at least 1 Giga Ohm, and wherein a gain of the first differential amplifier is less than 15.
19 . The amplification circuitry of claim 16 , further comprising:
a second differential amplifier having an input coupled to an output terminal of the first differential amplifier.
20 . The amplification circuitry of claim 19 , wherein the second differential amplifier is configured to be powered by dual-supply voltages.