Semiconductor devices and methods of handling data lifetime codes used therein
A semiconductor device includes a latch circuit and a code comparison circuit. The latch circuit latches an output code generated based on an active command. The latch circuit outputs the latched output code as a latch code in response to a write command. The code comparison circuit compares the latch code with a write code to generate a detection signal.
1. A semiconductor device comprising:
a latch circuit configured to latch an output code generated based on an active command and configured to output the latched output code as a latch code in response to a write command; and
a code comparison circuit configured to compare the latch code with a write code to generate a detection signal,
wherein the detection signal is enabled when a first data lifetime code set by the write code is set to be greater than a second data lifetime code set by the latch code and the first data lifetime code is updated by the second data lifetime code when the detection signal is enabled, and
wherein the first data lifetime code and the second data lifetime code differ from each other based upon respective combination of bank address and row address logic levels of storage selection areas.
2. The semiconductor device of claim 1 , wherein the output code is a data lifetime code corresponding to data selected by a bank address and a row address.
3. The semiconductor device of claim 1 , wherein the latch circuit includes: a first latch circuit configured to latch the output code if a data lifetime code corresponding to data stored in a first bank code storage circuit is outputted as the output code; and a second latch circuit configured to latch the output code if a data lifetime code corresponding to data stored in a second bank code storage circuit is outputted as the output code.
4. The semiconductor device of claim 3 , wherein the latch code includes a first latch code and a second latch code; wherein the first latch circuit outputs the latched output code as the first latch code if a write operation is performed; and wherein the second latch circuit outputs the latched output code as the second latch code if the write operation is performed.
5. The semiconductor device of claim 1 , wherein the latch circuit latches the write code if the detection signal is enabled.
6. The semiconductor device of claim 1 , wherein the latch circuit outputs the latched output code as an input code during a pre-charge operation; and wherein the input code is stored as a data lifetime code corresponding to data selected by an address.
7. A method of handling a data lifetime code, the method comprising:
latching an output code generated based on an active command; transforming the latched output code into a latch code based on a write command; and
comparing the latch code with a write code to generate a detection signal
wherein the detection signal is enabled when a first data lifetime code set by the write code is set to be greater than a second data lifetime code set by the latch code and the first data lifetime code is update by the second data lifetime code when the detection signal is enabled, and
wherein the first data lifetime code and the second data lifetime code differ from each other based upon respective combination of bank address and row address logic levels of storage selection areas.
8. The method of claim 7 , wherein the output code is a data lifetime code corresponding to data selected by a bank address and a row address.
9. The method of claim 7 , further comprising latching the write code if the detection signal is enabled.
10. The method of claim 7 , further comprising transforming the latched output code into an input code during a pre-charge operation, wherein the input code is stored as a data lifetime code corresponding to data selected by an address.
11. The semiconductor device of claim 1 , wherein the first data lifetime code and the second data lifetime code have logic level combination corresponding to lifetime of data.