IP Library Granted Patent US 10,445,246
Granted Patent B2
US 10,445,246 · App. 15/820,573 · Granted Oct 15, 2019

Memory system and method for controlling nonvolatile memory

Inventors: Hideki Yoshida (Yokohama Kanagawa, JP); Shinichi Kanno (Tokyo, JP)
Assignee: Toshiba Memory Corporation
G06F12/1009G06F2212/1016G06F2212/657
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Quick Facts
Patent No.
US 10,445,246
App. No.
15/820,573
Granted
Oct 15, 2019
Kind
B2
Abstract

According to one embodiment, a memory system receives a write request specifying a first logical address to which first data is to be written, and a length of the first data, from a host. The memory system writes the first data to a nonvolatile memory, and stores a first physical address indicating a physical storage location on the nonvolatile memory to which the first data is written, and the length of the first data, in an entry of a logical-to-physical address translation table corresponding to the first logical address. When the memory system receives a read request specifying the first logical address, the memory system acquires the first physical address and the length from the address translation table, and reads the first data from the nonvolatile memory.

Claims (27)

1. A memory system connectable to a host, the memory system comprising:

a nonvolatile memory; and

a controller electrically connected to the nonvolatile memory and configured to control the nonvolatile memory, wherein

the controller is further configured to:

manage a logical-to-physical address translation table including a plurality of entries corresponding to a plurality of logical addresses;

receive a write request specifying a first logical address to which first data is to be written, and a length of the first data, from the host;

write the first data to the nonvolatile memory;

store a first physical address indicating a physical storage location on. the nonvolatile memory to which the first data is written, and the length of the first data, in the entry of the logical-to-physical address translation table corresponding to the first logical address; and

when receiving a read request specifying the first logical address from the host, acquire the first physical address and the length from the logical-to-physical address translation table, and read the first data from the nonvolatile memory based on the acquired first physical address and the acquired length.

2. The memory system of claim 1 , wherein the physical storage location on the nonvolatile memory is represented by a block number in the nonvolatile memory and a location in a block.

3. The memory system of claim 1 , wherein the physical storage location on the nonvolatile memory is represented by a block number in the nonvolatile memory, a page number in a block, and a location in a page.

4. The memory system of claim 1 , wherein the first data is variable-length data in which a length of data corresponding to one logical address is variable.

5. The memory system of claim 1 , wherein

when a first data portion included in the first data is written to a first block in the nonvolatile memory, and a second data portion included in the first data is written to a second block in the nonvolatile memory,

the controller is further configured to store a first physical address, a length of the first data portion, a second physical address, and a length of the second data portion, in the entry of the logical-to-physical address translation table corresponding to the first logical address, the first physical address being indicating the physical storage location on the first block to which the first data portion is written, the second physical address being indicating the physical storage location on the second block to which the second data portion is written.

6. A method of controlling a nonvolatile memory, the method comprising:

managing a logical-to-physical address translation table including a plurality of entries corresponding to a plurality of logical addresses;

receiving a write request specifying a first logical address to which first data is to be written, and a length of the first data, from a host;

writing the first data to the nonvolatile memory;

storing a first physical address indicating a physical storage location on the nonvolatile memory to which the first data is written, the length of the first data, in the entry of the logical-to-physical address translation table corresponding to the first logical address; and

when receiving a read request specifying the first logical address from the host, acquiring the first physical address and the length from the logical-to-physical address translation table, and reading the first data from the nonvolatile memory based on the acquired first physical address and the acquired length.

7. The method of claim 6 , wherein the physical storage location on the nonvolatile memory is represented by a block number in the nonvolatile memory and a location in a block.

8. The method of claim 6 , wherein the physical storage location on the nonvolatile memory is represented by a block number in the nonvolatile memory, a page number in a block, and a location in a page.

9. The method of claim 6 , wherein the first data is variable-length data in which a length of data corresponding to one logical address is variable.

10. The method of claim 6 , further comprising,

when a first data portion included in the first data is written to a first block in the nonvolatile memory, and a second data portion included in the first data is written to a second block in the nonvolatile memory,

storing a first physical address, a length of the first data portion, a second physical address, and a length of the second data portion, in the entry of the logical-to-physical address translation table corresponding to the first logical address, the first physical address being indicating the physical storage location on the first block to which the first data portion is written, the second physical address being indicating the physical storage location on the second block to which the second data portion is written.

Assignments (4)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 22, 2017
From: YOSHIDA, HIDEKI; KANNO, SHINICHI
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 044197/0505 →
Priority Claims (1)
JP 2017-135785 · Jul 11, 2017 · national
Continuity (1)
Related Publication 20190018788A1 · Jan 17, 2019