Memory system including a delegate page and method of identifying a status of a memory system

1. A nonvolatile memory system comprising:

a nonvolatile memory device including at least one memory block including a plurality of storage pages and a delegate page;

a delegate page attacker configured for attacking a bit of the delegate page at the same corresponding location as a bit of the storage page in which an error occurs; and

a health status analyzer configured for performing write and read operations for the delegate page and analyzing error information occurred in the write and read operations to determine whether the nonvolatile memory device is in a failure status.

2. The nonvolatile memory system of claim 1 , wherein the nonvolatile memory device is a nonvolatile memory device capable of accessing in units of bits.

3. The nonvolatile memory system of claim 1 , wherein each of the storage pages in the memory block to which the delegate page is included and the delegate page include substantially the same memory cell structure.

4. The nonvolatile memory system of claim 1 , wherein each of the storage pages in the memory block to which the delegate page is included and the delegate page include the same storage capacity.

5. The nonvolatile memory system of claim 1 , wherein the nonvolatile memory device includes a plurality of memory blocks, and each of the memory blocks has the storage pages and the delegate page.

6. The nonvolatile memory system of claim 1 , wherein attacking the bit of the delegate page by the delegate page attacker includes repeatedly performing a write operation for inverting a value stored for the bit of the delegate page at the same location as the bit of the storage page in which the error occurred.

7. The nonvolatile memory system of claim 1 , wherein attacking the bit of the delegate page by the delegate page attacker includes repeatedly performing a write operation for writing specific data to the bit of the delegate page at the same corresponding location as the bit of the storage page in which the error occurred.

8. The nonvolatile memory system of claim 1 , wherein the health status analyzer performs when the nonvolatile memory device is in an idle status.

9. The nonvolatile memory system of claim 1 , wherein the health status analyzer comprises:

a data pattern generating unit generating a data pattern for performing write and read operations for the delegate page;

an error detecting unit detecting an error generated in a process of writing and reading the data pattern for the delegate page; and

an error analyzing unit analyzing the error detected by the error detecting unit to determine whether the nonvolatile memory device is in a failure status.

10. The nonvolatile memory system of claim 9 , wherein the data pattern is randomly configured or composed of a constant binary value of “0” or “1”.

11. The nonvolatile memory system of claim 9 , wherein the error detecting unit performs detecting the error in a state in which error correction is interrupted.

12. The nonvolatile memory system of claim 9 , wherein the error analyzing unit analyzes a number of bits and a degree of the error detected by the error detecting unit and determines whether the nonvolatile memory device is in a failure status.

13. A method of identifying an overall health status of a nonvolatile memory system comprising:

configuring at least one memory block of a nonvolatile memory device to include a plurality of storage pages and a delegate page;

attacking a bit of the delegate page at the same corresponding location as a bit of the storage page in which an error occurs, when the error occurs in write and read operations for the storage page of the nonvolatile memory device; and

identifying the overall health status of the nonvolatile memory device by performing write and read operations for the delegate page and analyzing error information generated in the write and read operations.

14. The method of identifying an overall health status of a nonvolatile memory system of claim 13 , wherein the nonvolatile memory device is capable of accessing in units of bits.

15. The method of identifying an overall health status of a nonvolatile memory system of claim 13 , wherein each of the storage pages and the delegate page include substantially the same memory cell structure.

16. The method of identifying an overall health status of a nonvolatile memory system of claim 13 , wherein attacking a bit of the delegate page includes repeatedly performing a write operation of inverting a value stored for a bit of the delegate page at the same corresponding location as a bit of the storage page in which the error occurs.

17. The method of identifying an overall health status of a nonvolatile memory system of claim 13 , wherein identifying the overall health status of the nonvolatile memory device is performed when the nonvolatile memory device is in an idle status.

18. The method of identifying an overall health status of a nonvolatile memory system of claim 13 , wherein identifying the overall health status of the nonvolatile memory device includes:

generating a data pattern for performing write and read operations for the delegate page;

detecting an error occurring in the write and read operations of the data pattern for the delegate page; and

analyzing the detected error to identify the overall health status of the nonvolatile memory device.

19. The method of identifying an overall health status of a nonvolatile memory system of claim 18 , wherein the data pattern is randomly configured or composed of a constant binary value of “0” or “1”.

20. The method of identifying an overall health status of a nonvolatile memory system of claim 18 , wherein analyzing the detected error is performed in a state in which error correction is interrupted.

21. The method of identifying an overall health status of a nonvolatile memory system of claim 19 , wherein analyzing the detected error is performed by analyzing a number of bits and a degree of the detected error to identify the overall health status of the nonvolatile memory device.