Semiconductor memory system
View Patent ↗According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
1. A method of constructing a semiconductor device, comprising:
forming a layer stack having a plurality of upper layers each having a metal pattern stacked on a plurality of lower layers each having a metal pattern with an insulating layer disposed between each adjacent two of the upper and lower layers, wherein a number of the upper layers is equal to a number of the lower layers and wherein a first metal pattern density of all of the lower layers and a second metal pattern density of the all of the upper layers are substantially equal; and
mounting a controller for controlling nonvolatile semiconductor memories on an uppermost one of the upper layers.
2. The method according to claim 1 , wherein:
the lower layers include a first layer having a signal wiring pattern sandwiched by second and third layers each of which includes a power supply plane or a ground plane.
3. The method according to claim 1 , comprising:
forming the upper layers to have first to fourth layers stacked in order with the first layer being the uppermost one of the upper layers and the fourth layer being the lowermost one of the upper layers; and
forming the second layer to have a third metal pattern density greater than the first metal pattern density.
4. The method according to claim 3 , comprising:
forming each of the first and third layers to have a metal pattern density lower than the first metal pattern density.
5. The method according to claim 1 , comprising:
forming the upper layers to have at least two layers being one of power supply layer and a ground layer.
6. The method according to claim 1 , comprising:
forming an uppermost one of the lower layers to have one of power supply pattern and a ground pattern; and
forming a layer directly below the uppermost one of the lower layers to be a signal layer.
7. The method according to claim 1 , comprising:
forming each of at least two layers of said upper layers to be a signal layer, and
forming said at least two layers be directly adjacent to each other.
8. A method of constructing a semiconductor device comprising:
forming a layer stack having a plurality of upper layers each having a metal pattern stacked on a plurality of lower layers each having a metal pattern with an insulating layer disposed between each adjacent two of the upper and lower layers, wherein a number of the upper layers is equal to a number of the lower layers and wherein a difference between a first metal pattern density of all of the lower layers and a second metal pattern density of the all of the upper layers is about 7.5% or less; and
mounting a controller for controlling nonvolatile semiconductor memories on an uppermost one of the upper layers.
9. The method according to claim 8 , wherein:
the lower layers include a first layer having a signal wiring pattern sandwiched by second and third layers each of which includes a power supply plane or a ground plane.
10. The method according to claim 8 , comprising:
forming the upper layers to have first to fourth layers stacked in order with the first layer being the uppermost one of the upper layers and the fourth layer being the lowermost one of the upper layers; and
forming the second layer to have a third metal pattern density greater than the first metal pattern density.
11. The method according to claim 10 , comprising:
forming each of the first and third layers to have a metal pattern density lower than the first metal pattern density.
12. The method according to claim 8 , comprising:
forming the upper layers to have at least two layers being one of power supply layer and a ground layer.
13. The method according to claim 8 , comprising:
forming an uppermost one of the lower layers to have one of power supply pattern and a ground pattern; and
forming a layer directly below the uppermost one of the lower layers to be a signal layer.
14. The method according to claim 8 , comprising:
forming each of at least two layers of said upper layers to be a signal layer, and
forming said at least two layers be directly adjacent to each other.