Non-planar field effect transistor devices with wrap-around source/drain contacts

1. A method for fabricating a semiconductor device comprising:

forming a nanowire stack structure on a semiconductor substrate, wherein the nanowire stack structure comprises a first sacrificial semiconductor layer disposed on the semiconductor substrate, a second sacrificial semiconductor layer disposed on the first sacrificial semiconductor layer, and a semiconductor channel layer disposed on the second sacrificial semiconductor layer;

forming a first isolation layer on the semiconductor substrate, wherein the first isolation layer comprises a thickness which is substantially equal to a thickness of the first sacrificial semiconductor layer of the nanowire stack structure;

forming a dummy gate structure over a portion of the nanowire stack structure;

etching exposed portions of the nanowire stack structure, which are not covered by the dummy gate structure, down to an upper surface of the first sacrificial semiconductor layer of the nanowire stack structure;

laterally recessing exposed sidewall surfaces of the second sacrificial semiconductor layer to form recesses in sidewalls of the nanowire stack structure, wherein the lateral recessing is performed by etching the second sacrificial semiconductor layer selective to the first sacrificial semiconductor layer and the semiconductor channel layer;

filling the recesses with dielectric material to form embedded gate sidewall spacers;

etching away the first sacrificial semiconductor layer of the nanowire stack structure to form an opening that is surrounded by the first isolation layer;

filling the opening with an insulating material to form a second isolation layer;

forming a first recess region in the first and second isolation layers on a first side of the gate structure, and forming a second recess region in the first and second isolation layers on the second side of the gate structure;

filling the first and second recess regions with a sacrificial material which has etch selectivity with respect to the first and second isolation layers, to form first and second dummy source/drain contact layers;

forming a first source/drain region and a second source/drain region over the first dummy source/drain contact layer and the second dummy source/drain contact layer, respectively;

replacing the dummy gate structure with a metal gate structure;

etching away the first and second dummy source/drain contact layers selective to the first and second isolation layers to form first and second recesses below the first and second source/drain regions; and

depositing a layer of metallic material to fill the first and second recesses with metallic material and form first and second source/drain contacts which surround the first and second source/drain regions, respectively.

2. The method of claim 1 , wherein the first source/drain contact is formed in contact with an upper surface, sidewalls surfaces, and the bottom surface of the first source/drain region, and wherein the second source/drain contact is formed in contact with an upper surface, sidewall surfaces, and the bottom surface of the second source/drain region.

3. The method of claim 1 , wherein forming the first source/drain region and the second source/drain region comprises epitaxially growing the first and second source/drain regions on portions of the semiconductor channel layer exposed on the sidewalls of the nanowire stack structure.

4. The method of claim 1 , wherein forming the nanowire stack structure on the semiconductor substrate comprises:

epitaxially growing the first sacrificial semiconductor layer on the semiconductor substrate;

epitaxially growing the second sacrificial semiconductor channel layer on the first sacrificial semiconductor layer;

epitaxially growing the semiconductor channel layer on the second sacrificial semiconductor layer; and

patterning the first and second sacrificial semiconductor layers and the semiconductor channel layer to form the nanowire stack structure.

5. The method of claim 1 , wherein the semiconductor channel layer comprises epitaxial silicon, wherein the second sacrificial semiconductor layer comprises silicon germanium with a first concentration of germanium, and wherein the first sacrificial semiconductor layer comprises silicon germanium with a second concentration of germanium, which is greater than the first concentration of germanium.

6. The method of claim 1 , wherein replacing the dummy gate structure with a metal gate structure comprises:

removing sacrificial gate material between insulating gate sidewall spacers to form a gate recess region;

selectively etching remaining portions of the second sacrificial semiconductor layer within the gate recess region to release the semiconductor channel layer within the gate recess region;

forming a conformal gate dielectric layer on exposed surfaces of the semiconductor channel layer within the gate recess region; and

depositing one or more layers of metallic material to fill the gate recess region;

wherein the one or more layers of metallic material comprises at least one of a work function metal layer and a gate electrode layer.