SIGNAL SELECTION CIRCUIT AND SEMICONDUCTOR DEVICE
Provided is a signal selection circuit including a control circuit capable of generating a drive signal having a fast rise/fall time. A positive feedback circuit is provided to the control circuit, which generates the drive signal for controlling a plurality of switches configured to switch an input signal to provide the signal to an output terminal.
1 . A signal selection circuit, comprising:
a first switch arranged between a first input terminal and a first output terminal;
a second switch arranged between a second input terminal and the first output terminal;
a third switch arranged between the first input terminal and a second output terminal;
a fourth switch arranged between the second input terminal and the second output terminal; and
a control circuit configured to
output a first control signal for controlling the first switch and the fourth switch, and a second control signal for controlling the second switch and the third switch by a clock signal provides from a clock input terminal,
the control circuit comprising:
a first inverter connected to the clock input terminal; and
a positive feedback circuit connected to both ends of the first inverter.
2 . A signal selection circuit according to claim 1 , wherein the positive feedback circuit comprises:
a first MOS transistor having a gate connected to an input terminal of the first inverter;
a second MOS transistor having a gate connected to an output terminal of the first inverter;
a second inverter having an input terminal connected to a drain of the first MOS transistor, and an output terminal connected to a drain of the second MOS transistor; and
a third inverter having an input terminal connected to the drain of the second MOS transistor, and an output terminal connected to the drain of the first MOS transistor.
3 . A semiconductor device, comprising the signal selection circuit of claim 1 .
4 . A semiconductor device, comprising the signal selection circuit of claim 2 .