Three-dimensional semiconductor memory device
View Patent ↗According to an embodiment, a semiconductor memory device comprises: a stacked body that includes a plurality of control gate electrodes stacked above a substrate; a memory columnar body that extends in a first direction above the substrate and configures a memory string along with the stacked body; and a source contact that extends in the first direction and is electrically connected to one end of the memory string. Moreover, this source contact is adjacent to the stacked body via a spacer insulating layer. Furthermore, a spacer protective layer including a nitride or a metal oxide is provided between these source contact and spacer insulating layer.
1. A semiconductor memory device comprising:
a plurality of control gate electrodes stacked in a first direction crossing a substrate;
a first semiconductor layer extending in the first direction;
a charge accumulation layer disposed between the control gate electrode and the first semiconductor layer;
a second semiconductor layer connected to one end of the first semiconductor layer and extending in a second direction crossing the first direction;
a source contact connected to the second semiconductor layer at its one end and extending in the first direction;
a first spacer insulating layer disposed between the plurality of control gate electrodes and the source contact; and
a second spacer insulating layer disposed between the source contact and the first spacer insulating layer and including a nitride or a metal oxide.
2. The semiconductor memory device according to claim 1 , wherein
the source contact comprises:
a first conductive layer extending in the first direction; and
a barrier metal layer provided between the first conductive layer and the second spacer insulating layer.
3. The semiconductor memory device according to claim 1 , wherein
the second spacer insulating layer includes silicon nitride (Si 3 N 4 ) or alumina (Al 2 O 3 ).
4. The semiconductor memory device according to claim 1 further comprising
a tunnel insulating layer disposed between the semiconductor layer and the control gate electrode.
5. The semiconductor memory device according to claim 4 further comprising
a block insulating layer disposed between the charge accumulation layer and the control gate electrode.
6. The semiconductor memory device according to claim 5 further comprising
first inter-layer insulating layers disposed between the control gate electrodes; and
a second inter-layer insulating layer provided above the control gate electrodes and the first inter-layer insulating layers, wherein
the block insulating layer is provided between the second inter-layer insulating layer and the source contact.
7. The semiconductor memory device according to claim 5 , wherein
the block insulating layer is divided in the first direction.
8. A semiconductor memory device comprising:
a plurality of control gate electrodes stacked in a first direction crossing a substrate;
a first semiconductor layer extending in the first direction;
a charge accumulation layer disposed between the control gate electrode and the first semiconductor layer;
a second semiconductor layer connected to one end of the first semiconductor layer and extending in a second direction crossing the first direction;
a source contact connected to the second semiconductor layer at its one end and extending in the first direction;
a first insulating layer disposed between the plurality of control gate electrodes and the source contact and extending in the first direction; and
a second insulating layer disposed between the source contact and the first insulating layer, the second insulating layer extending in the first direction and including a nitride or a metal oxide.
9. The semiconductor memory device according to claim 8 , wherein
the source contact comprises:
a first conductive layer extending in the first direction; and
a barrier metal layer provided between the first conductive layer and the second insulating layer.
10. The semiconductor memory device according to claim 8 , wherein
the second insulating layer includes silicon nitride (Si 3 N 4 ) or alumina (Al 2 O 3 ).
11. The semiconductor memory device according to claim 8 further comprising a tunnel insulating layer disposed between the semiconductor layer and the control gate electrode.
12. The semiconductor memory device according to claim 11 further comprising a block insulating layer disposed between the charge accumulation layer and the control gate electrode.
13. The semiconductor memory device according to claim 12 further comprising:
first inter-layer insulating layers disposed between the control gate electrodes; and
a second inter-layer insulating layer provided above the control gate electrodes and the first inter-layer insulating layers, wherein
the block insulating layer is provided between the second inter-layer insulating layer and the source contact.
14. The semiconductor memory device according to claim 12 , wherein
the block insulating layer is divided in the first direction.